AD7813YN Analog Devices Inc, AD7813YN Datasheet - Page 3

• Manufacturer Part Number: AD7813YN
• Description: IC ADC 10BIT PARALLEL 16-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7813YN

• Rohs Status: RoHS non-compliant
• Number Of Bits: 10
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)

TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
ABSOLUTE MAXIMUM RATINGS*
V
Digital Input Voltage to DGND
Digital Output Voltage to DGND
REF
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
REV. C
1
2
3
4
5
6
7
8
9
Sample tested to ensure compliance.
See Figures 12, 13 and 14.
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7813 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
POWER-UP
0.4 V or 2 V for V
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
of the part and as such is independent of external bus loading capacitances.
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
3
3, 4
3
DD
(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, V
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, V
θ
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
θ
Lead Temperature, Soldering
θ
Lead Temperature, Soldering
JA
JA
JA
IN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
1.5
2.3
20
30
0
0
10
10
5
10
50
DD
= 3 V ± 10%.
= 3 V
10%
V
1.5
2.3
20
30
0
0
10
10
5
10
50
DD
1, 2
= 5 V
(–40 C to +105 C, unless otherwise noted)
10%
DD
DD
DD
DD
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
Unit
µs (max)
µs (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
–3–
Model
AD7813YN
AD7813YR
AD7813YRU ± 1 LSB
Figure 1. Load Circuit for Digital Output Timing
Specifications
Conditions/Comments
Power-Up Time of AD7813 after Rising Edge of CONVST.
Conversion Time.
CONVST Pulsewidth.
CONVST Falling Edge to BUSY Rising Edge Delay.
CS to RD Setup Time.
CS Hold Time after RD High.
Data Access Time after RD Low.
Bus Relinquish Time after RD High.
Minimum Time Between MSB and LSB Reads.
Rising Edge of CS or RD to Falling Edge of CONVST Delay.
7
, quoted in the Timing Characteristics is the true bus relinquish time
OUTPUT
Linearity Package
Error
± 1 LSB
± 1 LSB
PIN
TO
50pF
ORDERING GUIDE
C
L
200 A
200 A
Description
Plastic DIP
Small Outline IC
Thin Shrink Small Outline RU-16
(TSSOP)
WARNING!
I
I
OL
OH
DD
ESD SENSITIVE DEVICE
= 5 V ± 10% and
1.6V
AD7813
Package
Option
N-16
R-16A