AD7476AAKS-500RL7 Analog Devices Inc, AD7476AAKS-500RL7 Datasheet - Page 22
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AD7476AAKS-500RL7
Manufacturer Part Number
AD7476AAKS-500RL7
Description
IC ADC 12BIT 1MSPS SC70-6 T/R
Manufacturer
Analog Devices Inc
Datasheet
1.AD7477AARMZ.pdf
(28 pages)
Specifications of AD7476AAKS-500RL7
Rohs Status
RoHS non-compliant
Design Resources
Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
17.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
6-TSSOP, SC-88, SOT-363
For Use With
EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
AD7476A/AD7477A/AD7478A
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
serial clock has the first leading zero provided and also clocks
out the second leading zero. For the AD7476A, the final bit in
the data transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK clocks out the second leading zero, which can be read in
the first rising edge. However, the first leading zero that was
clocked out when CS went low will be missed, unless it was not
read in the first falling edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after one SCLK falling edge has elapsed, CS
clocks out the first leading zero as it did before, and it can be
read in the SCLK rising edge. The next SCLK falling edge clocks
out the second leading zero, and it can be read in the following
rising edge.
SDATA
THREE-STATE
SCLK
CS
t
2
Z
1
ZERO
4 LEADING ZEROS
2
ZERO
Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface
3
ZERO
10.5(1/
t
CONVERT
4
f
SCLK
1/THROUGHPUT
DB7
Rev. F | Page 22 of 28
)
5
DB6
AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE
For the AD7478A, if CS is brought high in the 12th rising edge
after four leading zeros and eight bits of the conversion have
been provided, the part can achieve a 1.2 MSPS throughput
rate. For the AD7478A, the track-and-hold goes back into track
in the 11th rising edge. In this case, a f
throughput of 1.2 MSPS give a cycle time of
With t
satisfies the requirement of 225 ns for t
From Figure 27, t
where t
This allows a value of 237 ns for t
requirement of 50 ns.
t
0.5 (1/f
2
11
2
+ 10.5(1/f
8
= 10 ns min, this leaves t
B
= 36 ns maximum.
DB0
SCLK
t
8
12
) + t
SCLK
ACQ
8
)+ t
THREE-STATE
+ t
is comprised of
ACQ
QUIET
t
ACQ
t
QUIET
= 833 ns
t
1
ACQ
QUIET
to be 298 ns. This 298 ns
, satisfying the minimum
SCLK
ACQ
.
= 20 MHz and a