AD6644AST-65 Analog Devices Inc, AD6644AST-65 Datasheet
AD6644AST-65
Specifications of AD6644AST-65
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AD6644AST-65 Summary of contents
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FEATURES 65 MSPS guaranteed sample rate 40 MSPS version available Sampling jitter < 300 fs 100 dB multitone SFDR 1.3 W power dissipation Differential analog inputs Pin compatible to AD6645 Twos complement digital output format 3.3 V CMOS compatible Data-ready ...
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AD6644 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 Switching Specifications .............................................................. 4 ...
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... Full V 2.2 Full V 25°C V 1.5 Full II 4.85 5.0 Full II 3.0 3.3 Full II 245 Full II 30 Full IV Full II 1.3 Rev Page AD6644AST-65 Max Min Typ 14 Guaranteed +10 −10 +3 +10 −10 –6 +1.5 −1.0 ±0.25 ±0. ±1.0 2.4 2 1.5 5.25 4.85 5.0 3.6 3 ...
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... Min Typ 0 2.5 2.5 CMOS CMOS 2.5 2.5 0.4 0.4 Twos complement –25° +85°C, unless otherwise noted. MIN MAX AD6644AST-65 Typ Max Min Typ Max 6.5 6.5 = −25° +85°C, C MIN MAX LOAD AD6644AST-40/65 1 Min Typ 15.4 25 6.2 7.7 6.2 7 ...
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... To calculate t ENC −9 −9 + 8.6 × 13.4 × −9 −9 = 10.3 × −25° +85°C, unless otherwise noted. MIN MAX AD6644AST-40 AD6644AST-65 1 Min Typ Max Min Typ 74.5 74.5 74.0 72 74.0 73.5 72 73.5 74.5 74.5 74 ...
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AD6644 TIMING DIAGRAM AIN ENCODE, ENCODE t E_RL D[13:0], OVR DRY ENCH ENCL t ENC E_FL E_DR N – 3 ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AV Voltage CC DV Voltage CC Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Lead Temperature (Soldering, 10 sec) Maximum ...
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AD6644 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNC = DO NOT CONNECT Table 8. Pin Function Descriptions Pin Number 1, 33 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 ENCODE = 65MSPS –10 AIN = 2.2MHz @ –1dBFS SNR = 74.5dB –20 SFDR = 92dBc –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 4. ...
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AD6644 100 ENCODE = 65MSPS 95 WORST OTHER SPUR AIN = –1dBFS HARMONICS (SECOND, THIRD ANALOG FREQUENCY (MHz) Figure 10. Harmonics vs. Analog Frequency (IF) ...
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ENCODE = 65MSPS –10 AIN = 15.5MHz @ –29.5dBFS NO DITHER –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 16. 1M FFT Without Dither 100 ENCODE ...
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AD6644 EQUIVALENT CIRCUITS AIN BUF 500Ω BUF 500Ω AIN BUF V CL Figure 21. Analog Input Stage LOADS 10kΩ ENCODE 10kΩ LOADS Figure 22. ENCODE/ ENCODE ...
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TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...
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AD6644 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Reported in either dBc (that is, degrades ...
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THEORY OF OPERATION The AD6644 analog-to-digital converter (ADC) employs a three-stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. As shown in the functional block diagram, the AD6644 has ...
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AD6644 input matches Ω source with a full-scale drive of 4.8 dBm. Series resistors ( the secondary side of the S transformer should be used to isolate the transformer from the ADC. This limits the ...
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Jitter Considerations The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms ...
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AD6644 EVALUATION BOARD The schematic of the evaluation board (see Figure 32) repre- sents a typical implementation of the AD6644. A multilayer board is recommended to achieve best results highly recommended that high quality, ceramic chip capacitors be ...
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D4 C AVC +3P3V C DVC AVC D10 C AVC D11 D GN D12 C AVC D13 ...
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AD6644 Figure 33. Top Signal Level Figure 34. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4 Figure 35. Ground Plane Layer 2 and Ground Plane Layer 5 Figure 36. Bottom Signal Layer Rev Page 20 ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD6644AST-40 −25°C to +85°C 1 AD6644ASTZ-40 −25°C to +85°C AD6644AST-65 −25°C to +85°C 1 AD6644ASTZ-65 −25°C to +85°C AD6644ST/PCB 1 AD6644ST/PCBZ RoHS Compliant Part. 12.20 12.00 SQ 0.75 11.80 1 ...
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AD6644 NOTES Rev Page ...
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NOTES Rev Page AD6644 ...
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AD6644 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00971-0-8/07(D) Rev Page ...