MAX1185ECM+TD Maxim Integrated Products, MAX1185ECM+TD Datasheet - Page 5

• Manufacturer Part Number: MAX1185ECM+TD
• Description: IC ADC 10BIT 20MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1185ECM+TD

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Number Of Converters: 2
• Power Dissipation (max): 2.43W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
10kΩ resistor, V
otherwise noted. Typical values are at T
Note 1: Equivalent dynamic performance is obtainable over full OV
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
Note 5: Digital outputs settle to V
Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down.
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
Internal Reference and Multiplexed Parallel Outputs
DD
= 3V, OV
input voltage range.
6dB or better, if referenced to the two-tone envelope.
PARAMETER
DD
IN
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
= 2Vp-p (differential w.r.t. COM), C
_______________________________________________________________________________________
IH
, V
SYMBOL
t
t
DISABLE
ENABLE
PDISS
IL
I
t
OV
PSRR
t
OVDD
t
t
WAKE
I
V
A
DA/B
DOA
DOB
VDD
t
. Parameter guaranteed by design.
t
CH
CL
DD
= +25°C.) (Note 2)
DD
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, C
f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Offset
Gain
Figure 3 (Note 5)
Figure 3 (Note 5)
Figure 4
Figure 4
Figure 3, clock period: 50ns
Figure 3, clock period: 50ns
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
f
f
f
INA or B
INA or B
INA or B
INA or B
L
= 10pF at digital outputs (Note 1), f
= 7.5MHz at -0.5dBFS
= 7.5MHz at -0.5dBFS
= 7.5MHz at -0.5dBFS
= 7.5MHz at -0.5dBFS
INA or B
INA or B
L
= 15pF,
CONDITIONS
DD
= 7.5MHz at -0.5dBFS
= 7.5MHz at -0.5dBFS
range with reduced C
DD
DD
DD
CLK
L
.
= 20MHz, T
MIN
2.7
1.7
25 ± 7.5
25 ± 7.5
TYP
±0.2
±0.1
0.51
0.02
0.25
A
100
105
-70
3.0
2.5
2.8
8.4
1.5
1.5
35
10
1
9
2
3
5
5
6
= T
MIN
MAX
±0.2
150
to T
3.6
3.6
50
15
10
45
8
8
MAX
D eg r ees
, unless
UNITS
mV/V
%/V
mW
mA
mA
µW
µA
µA
dB
dB
ns
ns
ns
ns
ns
ns
ns
µs
V
V
5