AS1524-BTDT austriamicrosystems, AS1524-BTDT Datasheet - Page 15

• Manufacturer Part Number: AS1524-BTDT
• Description: IC ADC 12BIT 1CH 150K 8-TDFN
• Manufacturer: austriamicrosystems

Specifications of AS1524-BTDT

• Number Of Bits: 12
• Sampling Rate (per Second): 150k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AS1524/AS1525
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
Automatic Shutdown Mode
With CNVST low, the AS1524/AS1525 default to automatic shutdown (< 0.2µA) mode after power-up and between
conversions. After detecting a rising edge of CNVST, the AS1524/AS1525 powers up, sets DOUT low, and enters
track mode.
After detecting a falling edge of CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7µs
later, the device completes conversion, enters shutdown, and MSB is available at DOUT.
External Reference
An external reference is required for the AS1524/AS1525. Use a 4.7µF bypass capacitor for best performance. The
reference input structure allows a voltage range of +1V to V
Performing a Conversion
Standard Interface Connections
The AS1524/AS1525 serial interface is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is avail-
able, establish the processor’s serial interface as a master so that the CPU generates the serial clock for the AS1524/
AS1525 and select a clock frequency up to 8MHz.
SPI and Microwire Interface
When using an SPI
essary to obtain the entire 12-bit result from the AS1524/AS1525. DOUT data transitions on the serial clock’s falling
edge and is clocked into the processor on SCLK’s rising edge. The first 8-bit data stream contains the first 8-bits of
DOUT starting with the MSB. The second 8-bit data stream contains the remaining four result bits. DOUT then goes
high impedance.
Figure 23. SPI Serial Interface Connections
www.austriamicrosystems.com
1. Use a general-purpose I/O line on the CPU to hold CNVST low between conversions.
2. Drive CNVST high to acquire AIN1(AS1525) or unipolar mode (AS1524). To acquire AIN2 (AS1525) or bipolar
3. Hold CNVST high for 1.4µs.
4. Drive CNVST low and wait approximately 3.7µs for conversion to complete. After 3.7µs, the MSB is available
5. Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK’s falling edge and is avail-
mode (AS1524), drive CNVST low and high again.
at DOUT.
able in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the µP on
SCLK’s rising edge.
(Figure
23) or Microwire interface
SSM
CPU
Revision 1.02
(Figure
SCK
I/O
MISO
DD
24), set CPOL = CPHA = 0. Two 8-bit readings are nec-
+ 50mV.
CNVST
DOUT
SCLK
8
6
7
AS1524/
AS1525
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