AS1538-BTST austriamicrosystems, AS1538-BTST Datasheet - Page 12

• Manufacturer Part Number: AS1538-BTST
• Description: IC ADC 12BIT 8CH 50K 16-TSSOP
• Manufacturer: austriamicrosystems

Specifications of AS1538-BTST

• Number Of Bits: 12
• Sampling Rate (per Second): 50k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AS1538/AS1540
Data Sheet - D e t a i l e d D e s c r i p t i o n
Figure 24 on page 11
bit, two types of data transfer are possible:
The AS1538 can operate in the following slave modes:
Address Byte
The address byte
Figure 25. Address Byte
Following the START condition, the AS1538 monitors the SDA bus, checking the device type identifier being transmit-
ted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an
acknowledge signal on the SDA line.
Command Byte
The AS1538/AS1540 operation, including powerdown
by a command byte
Figure 26. Command Byte
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- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by
- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave
- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an
- Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver
- The first five bits (MSBs) of the slave address are factory-set to 10010.
- The next two bits of the address byte are the device select bits, A1 and A0, which are set by the state of pins A1
- The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is
bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line HIGH to enable the master to generate the STOP condition.
a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte.
then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received
byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START
and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a
repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.
mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is
transmitted on SDA by the AS1538 while the serial clock is input on SCL. START and STOP conditions are rec-
ognized as the beginning and end of a serial transfer.
and A0 at startup. A maximum of four devices with the same pre-set code can therefore be connected on the
same bus at one time. Pins A1/A0 can be connected to +V
selected; when set to a 0 a write operation is selected.
(see Figure 25)
(see Figure
details how data transfer is accomplished on the I
MSB
MSB
SD
1
26).
is the first byte received following the START condition from the master device.
C2
6
0
6
C1
5
0
5
Revision 1.03
(see Table 5)
C0
4
1
4
PD1
3
0
3
DD
or digital ground.
and channel selection
PD0
A1
2
2
2
C bus. Depending upon the state of the R/W
A0
X
1
1
LSB
R/W
LSB
X
(see Table 6)
is determined
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