AD7621ASTZ Analog Devices Inc, AD7621ASTZ Datasheet - Page 5

IC ADC 16BIT 2MSPS DIFF 48-LQFP

AD7621ASTZ

Manufacturer Part Number
AD7621ASTZ
Description
IC ADC 16BIT 2MSPS DIFF 48-LQFP
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of AD7621ASTZ

Data Interface
Serial, Parallel
Number Of Bits
16
Sampling Rate (per Second)
2M
Number Of Converters
1
Power Dissipation (max)
86mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
16bit
Sampling Rate
3MSPS
Input Channel Type
Differential
Supply Current
25.2mA
Digital Ic Case Style
QFP
No. Of Pins
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7621CBZ - BOARD EVALUATION FOR AD7621
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7621ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7621ASTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7621ASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35)
MASTER SERIAL INTERFACE MODES
Convert Pulse Width
Time Between Conversions (Warp
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode)
RESET Pulse Width
RESET Low to BUSY High Delay
BUSY High Time from RESET Low
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert
CNVST Low to SYNC Asserted Delay (All Modes)
SYNC Deasserted to BUSY Low Delay
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
6
6
6
6
6
6
4
4
5
2
(Refer to Figure 37 and Figure 38)
Mode/Normal Mode/Impulse Mode)
5
6
REF
= 2.5 V; all specifications T
Rev. 0 | Page 5 of 32
3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
38
39
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MIN
to T
Min
15
333/500/800
10
50/70/50
15
2
2
0.5
8
2
3
1
0
0
MAX
, unless otherwise noted.
Typ
1
10
600
12/137/263
See Table 4
275/400/500
13
Max
70
23
283/430/560
283/430/560
283/430/560
20
15
10
10
10
12
10
10
10
1
AD7621
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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