AD7710AR Analog Devices Inc, AD7710AR Datasheet - Page 25

• Manufacturer Part Number: AD7710AR
• Description: IC ADC 24BIT DIFF INP 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7710AR

• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Peak Reflow Compatible (260 C): No
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Features: 24-Bit, Signal Conditioning W/2 Diff. In Ch.
• No. Of Channels: 2
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REV. G
AD7710 to 8XC51 Interface
Figure 17 shows an interface between the AD7710 and the 8XC51
microcontroller. The AD7710 is configured for external clock-
ing mode, while the 8XC51 is configured in its Mode 0 serial
interface mode. The DRDY line from the AD7710 is connected
to the Port P1.2 input of the 8XC51, so the DRDY line is polled
by the 8XC51. The DRDY line can be connected to the INT1
input of the 8XC51 if an interrupt driven system is preferred.
Figure 16. Flowchart for Single Write Operation
to the AD7710
8XC51
Figure 17. AD7710 to 8XC51 Interface
P1.0
P1.2
P1.3
P3.0
P1.1
P3.1
ACCUMULATOR TO
WRITE DATA FROM
LOAD DATA FROM
RFS, TFS, AND A0
TFS AND A0 HIGH
TFS AND A0 LOW
CONFIGURE AND
INITIALIZE C/ P
SERIAL BUFFER
ACCUMULATOR
SERIAL PORT
ADDRESS TO
ORDER OF
REVERSE
START
BRING
BRING
BRING
HIGH
BITS
END
DV
DD
3
DRDY
MODE
SYNC
RFS
TFS
A0
SDATA
SCLK
AD7710
–25–
Table VII shows some typical 8XC51 code used for a single 24-bit
read from the output register of the AD7710. Table VIII shows
some typical code for a single write operation to the control register
of the AD7710. The 8XC51 outputs the LSB first in a write
operation, while the AD7710 expects the MSB first so the data to
be transmitted has to be rearranged before being written to the
output serial register. Similarly, the AD7710 outputs the MSB first
during a read operation, while the 8XC51 expects the LSB first.
Therefore, the data that is read into the serial buffer needs to be
rearranged before the correct data-word from the AD7710 is
available in the accumulator.
WAIT:
READ:
POLL:
READ 1:
END:
FIN:
MOV SCON,#00010001B; Configure 8051 for MODE 0
MOV IE,#00010000B;
SETB 90H;
SETB 91H;
SETB 93H;
MOV R1,#003H;
MOV R0,#030H;
MOV R6,#004H;
NOP;
MOV A,P1;
ANL A,R6;
JZ READ;
SJMP WAIT;
CLR 90H;
CLR 98H;
JB 98H, READ1
SJMP POLL
MOV A,SBUF;
RLC A;
MOV B.0,C;
SETB 90H
SJMP FIN
RLC A; MOV B.1,C; RLC A; MOV B.2,C;
RLC A; MOV B.3,C; RLC A; MOV B.4,C;
RLC A; MOV B.5,C; RLC A; MOV B.6,C;
RLC A; MOV B.7,C;
MOV A,B;
MOV @R0,A;
INC R0;
DEC R1
MOV A,R1
JZ END
JMP WAIT
Table VII. 8XC51 Code for Reading from the AD7710
Disable All Interrupts
Set P1.0, Used as RFS
Set P1.1, Used as TFS
Set P1.3, Used as A0
Sets Number of Bytes to Be Read in
a Read Operation
Start Address for Where Bytes Will
Be Loaded
Use P1.2 as DRDY
Read Port 1
Mask Out All Bits Except DRDY
If Zero Read
Otherwise Keep Polling
Bring RFS Low
Clear Receive Flag
Tests Receive Interrupt Flag
Read Buffer
Rearrange Data
Reverse Order of Bits
Write Data to Memory
Increment Memory Location
Decrement Byte Counter
Jump if Zero
Fetch Next Byte
Bring RFS High
AD7710