AD7720BRU Analog Devices Inc, AD7720BRU Datasheet - Page 12

• Manufacturer Part Number: AD7720BRU
• Description: IC MODULATOR SIGMA-DELTA 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7720BRU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 12.5M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 215mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)

AD7720
The 1 nF capacitors at each ADC input store charge to aid the
amplifier settling as the input is continuously switched. A resis-
tor in series with the drive amplifier output and the 1 nF input
capacitor may also be used to create an antialias filter.
Clock Generation
The AD7720 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with the crystal is shown
in Figure 30. Consult the crystal manufacturer’s recommenda-
tion for the load capacitors.
Figure 28. Single-Ended Analog Input for Bipolar Mode
Operation
AIN =
1.25V
0.625V
Figure 29. Single-Ended to Differential Analog Input
Circuit for Bipolar Mode Operation
AIN =
1k
1k
1k
1k
R
R
OP275
12pF
OP275
12pF
1/2
1/2
1k
1k
1k
1k
OP275
1/2
12pF
374k
374k
OP275
12pF
OP07
1/2
1k
100nF
220nF
220nF
100nF
1nF
1nF
1nF
1nF
10nF
VIN(–)
DIFFERENTIAL
INPUT = 2.5V p-p
VIN(+)
REF1
REF2
COMMON MODE
VOLTAGE = 2.5V
DIFFERENTIAL
INPUT = 2.5V p-p
VIN(+)
VIN(–)
VIN(–) BIAS
VOLTAGE = 1.25V
REF1
REF2
–12–
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the sam-
pling process. The connection diagram for an external clock
source (Figure 31) shows a series damping resistor connected
between the clock output and the clock input to the AD7720.
The optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
A low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively modu-
lates the input signal and raises the noise floor. The sampling
clock generator should be isolated from noisy digital circuits,
grounded and heavily decoupled to the analog ground plane.
The sampling clock generator should be referenced to the ana-
log ground plane in a split ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital plane to the AD7720 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. The jitter can cause unwanted
degradation in the signal-to-noise ratio and also produce un-
wanted harmonics.
This can be somewhat remedied by transmitting the sampling
clock signal as a differential one, using either a small RF trans-
former or a high speed differential driver and receiver such as
PECL. In either case, the original master system clock should
be generated from a low phase noise crystal oscillator.
Figure 31. External Clock Oscillator Connection
Figure 30. Crystal Oscillator Connection
CIRCUITRY
CLOCK
XTAL
25–150
1M
MCLK
MCLK
REV. 0