AD7738BRU Analog Devices Inc, AD7738BRU Datasheet - Page 18

• Manufacturer Part Number: AD7738BRU
• Description: IC ADC 24BIT 8-CH 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7738BRU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 15.4k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• For Use With: EVAL-AD7738EBZ - BOARD EVAL FOR AD7738

AD7738
Mode Register
8 Bits Read/Write Register, Address 38h–3Fh, Default Value 00h
The Mode register configures the part and determines the part’s operating mode. Writing to the Mode register will clear the ADC
Status register, set the RDY pin to logic high level, exit all current operations, and start the mode specified by the Mode bits.
The AD7738 contains only one Mode register. The three LSBs of the address used for writing to the Mode register specify the channel
selected for operation determined by the MD2 to MD0 bits. The address 38h only must be used for reading from the Mode register.
Bit
Mnemonic
Default
Bit
7–5
4
3
2
1
0
MD2 MD1 MD0 Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Mnemonic
MD2–MD0
CLKDIS
DUMP
CONT RD
24/16 BIT
CLAMP
0
1
0
1
0
1
0
1
Bit 7
MD2
0
Idle Mode
Continuous Conversion Mode
Single Conversion Mode
Power Down (Standby) Mode
ADC Zero-Scale Self Calibration
For Future Use
Channel Zero-Scale System Calibration
Channel Full-Scale System Calibration
Description
Mode Bits. These three bits determine the AD7738 operation mode. Writing a new value to the Mode
bits will exit the part from the mode in which it has been operating and place it in the new requested
mode immediately. The function of the Mode bits is described in more detail below.
Master Clock Output Disable. When this bit is set to 1 the master clock is disabled from appearing
at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the
MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7738
continues to have internal clocks and will convert normally regardless of CLKDIS bit state. When using
a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7738 clock is
stopped and no conversions can take place when the CLKDIS bit is active. The AD7738 digital interface
can still be accessed using the SCLK pin.
DUMP Mode. When this bit is reset to 0, the Channel Status register and Channel Data register will
be addressed and read separately. When the DUMP bit is set to 1, the Channel Status register will be followed
immediately by a read of the Channel Data register regardless of whether the Status or Data register
has been addressed through the Communication register. The Continuous Read mode will always be a
“Dump Mode” reading of the Channel Status and Data register regardless of the Dump Bit value. See the
Digital Interface Description section for more details.
When this bit is set to 1, the AD7738 will operate in the Continuous Read mode. See the Digital
Interface Description section for more details.
The Channel Data Register Data Width Selection Bit. When set to 1, the Channel Data registers will be
24 bits wide. When set to 0, then the Channel Data registers will be 16 bits wide.
This bit determines the Channel Data register’s value when the analog input voltage is outside the nominal
input voltage range. When the CLAMP bit is set to 1, the Channel Data register will be digitally clamped
either to all zeros or all ones when the analog input voltage goes outside the nominal input voltage range.
When the CLAMP bit is reset to 0, the Data registers reflect the analog input voltage even outside the
nominal voltage range. See the Analog Inputs Extended Voltage Range section.
Bit 6
MD1
0
Bit 5
MD0
0
CLKDIS
Bit 4
0
–18–
Address Used for Mode Register Write Specify
The First Channel to Start Converting
Channel to Convert
Channel Conversion Time Used for the ADC Self-Calibration
Channel to Calibrate
Channel to Calibrate
DUMP
Bit 3
0
Bit 2
CONT RD
0
Bit 1
24/16 BIT
0
Bit 0
CLAMP
0
REV. 0