AD7694BRMZ Analog Devices Inc, AD7694BRMZ Datasheet - Page 12

• Manufacturer Part Number: AD7694BRMZ
• Description: IC ADC 16BIT SAR 250KSPS 8MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7694BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 6.3mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Current: 800µA
• No. Of Pins: 8
• Operating: RoHS Compliant
• Sampling Rate: 250kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7694CBZ - BOARD EVALUATION FOR AD7694
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7694
APPLICATION INFORMATION
CIRCUIT INFORMATION
The AD7694 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of con-
verting 250,000 samples per second (250 kSPS) and powers
down between conversions. When operating at 100 SPS, for
example, it typically consumes 4 μW, ideal for battery-powered
applications.
The AD7694 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7694 is specified from 2.7 V to 5.25 V. It is housed in an
8-lead MSOP. The AD7694 is an improved second source to
LTC1864 and LTC1864L. For even better performance, the
AD7685
CONVERTER OPERATION
The AD7694 is a successive approximation ADC based on a
charge redistribution DAC. Figure 18 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase begins. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Thus, the differential voltage between the inputs, IN+
and IN−, captured at the end of the acquisition phase applies to
the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (V
control logic toggles these switches, starting with the MSB, in
order to bring the comparator back into a balanced condition.
should be considered.
GND
REF
IN+
IN–
REF
/2, V
REF
/4 … V
32,768C
32,768C
REF
/65536). The
16,384C
16,384C
MSB
MSB
Figure 18. ADC Simplified Schematic
4C
4C
Rev. A | Page 12 of 16
2C
2C
C
C
After the completion of this process, the part returns to the
acquisition phase and the control logic generates the ADC
output code.
Because the AD7694 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7694 is shown in
Figure 19 and Table 8.
Table 8. Output Codes and Ideal Input Voltages
Description
FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
1
2
This is also the code for an overranged analog input (V
V
This is also the code for an underranged analog input (V
REF
– V
C
C
GND
111...111
111...110
111...101
000...010
000...001
000...000
).
LSB
LSB
–FS + 0.5 LSB
–FS
SW+
SW–
Figure 19. ADC Ideal Transfer Function
COMP
–FS + 1 LSB
Analog Input
V
4.999924 V
2.499924 V
76.3 μV
0 V
2.500076 V
2.5 V
SWITCHES CONTROL
REF
= 5 V
CONTROL
LOGIC
CNV
ANALOG INPUT
Digital Output Code
Hexadecimal
FFFF
8001
8000
7FFF
0001
0000
BUSY
+FS – 1.5 LSB
OUTPUT CODE
1
2
IN+
+ FS – 1 LSB
IN+
– V
– V
IN–
IN–
above
below V
GND
).