AD7934BRUZ Analog Devices Inc, AD7934BRUZ Datasheet - Page 23

• Manufacturer Part Number: AD7934BRUZ
• Description: IC ADC 12BIT 4CH 1.5MSPS 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7934BRUZ

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 1.5M
• Number Of Converters: 1
• Power Dissipation (max): 13.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analogue: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 1.5MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PARALLEL INTERFACE
The AD7933/AD7934 have a flexible, high speed, parallel
interface. This interface is 10 bits (AD7933) or 12 bits (AD7934)
wide and is capable of operating in either word (W/ B tied high)
or byte (W/ B tied low) mode. The CONVST signal is used to
initiate conversions and, when operating in autoshutdown or
autostandby mode, it is used to initiate power-up.
A falling edge on the CONVST signal is used to initiate
conversions, and it also puts the ADC track-and-hold into
track. Once the CONVST signal goes low, the BUSY signal goes
high for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t
must happen after the 14
conversion is aborted and the track-and-hold goes back into track.
TRACK/HOLD
DB0 TO DB11
DB0 TO DB11
INTERNAL
CONVST
CLKIN
Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/ B = 1)
BUSY
th
falling edge of CLKIN; otherwise, the
RD
CS
WITH CS AND RD TIED LOW
t
2
t
3
1
2
THREE-STATE
OLD DATA
3
4
1
. This
t
CONVERT
Rev. B | Page 23 of 32
5
12
A
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 10 bits or 12 bits of
conversion data. When power supplies are first applied to the
device, a rising edge on CONVST is necessary to put the track-
and-hold into track. The acquisition time of 125 ns minimum
must be allowed before CONVST is brought low to initiate a
conversion. The ADC then goes into hold on the falling edge of
CONVST and back into track on the 13
after this (see Figure 34). When operating the device in
autoshutdown or autostandby mode, where the ADC powers
down at the end of each conversion, a rising edge on the
CONVST signal is used to power up the device.
13
t
B
10
t
9
14
t
20
t
13
t
12
t
DATA
DATA
ACQUISITION
t
1
THREE-STATE
t
t
11
14
t
QUIET
AD7933/AD7934
th
rising edge of CLKIN