CS5351-BZZ Cirrus Logic Inc, CS5351-BZZ Datasheet - Page 23

• Manufacturer Part Number: CS5351-BZZ
• Description: IC ADC AUD 108DB 204KHZ 24-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5351-BZZ

• Package / Case: 24-TSSOP
• Number Of Bits: 24
• Sampling Rate (per Second): 204k
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 243mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPs
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1781 - EVALUATION BOARD FOR CS5351
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1084-5

DS565F2
7. REVISION HISTORY
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to
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to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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Release
PP2
F1
F2
Preliminary datasheet.
Improve Gain Error specification under Analog Characteristics.
Specify Full-scale Input Voltage in terms of VA under Analog Characteristics.
Update Differential Input Impedance under Analog Characteristics.
Increase maximum Power-Supply Current, I
Reduce maximum Power Consumption under DC Electrical Characteristics.
Update FILT+ Output Impedance specification under DC Electrical Characteristics.
Extend maximum Fs in Single-Speed Mode to 51 kHz.
Extend maximum Fs in Double-Speed Mode to 102 kHz.
Extend maximum Fs in Quad-Speed Mode to 204 kHz.
Decrease maximum SCLK falling to LRCK edge specification in Quad-Speed Mode.
Replace minimum MCLK high/low timing specifications with duty cycle specification.
Replace minimum SCLK high/low timing specifications with duty cycle specification.
Replace recommended analog input buffer with new input buffer topology.
Updated ordering information.
www.cirrus.com.
A
, under DC Electrical Characteristics.
Changes
CS5351
23