AD7495AR-REEL Analog Devices Inc, AD7495AR-REEL Datasheet - Page 16
![IC ADC 12BIT SRL LP W/REF 8-SOIC](/photos/5/66/56684/505-8-soic_sml.jpg)
AD7495AR-REEL
Manufacturer Part Number
AD7495AR-REEL
Description
IC ADC 12BIT SRL LP W/REF 8-SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD7475ARMZ-REEL7.pdf
(24 pages)
Specifications of AD7495AR-REEL
Rohs Status
RoHS non-compliant
Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
10.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
AD7475/AD7495
OPERATING MODES
The AD7475/AD7495 operating mode is selected by controlling
the logic state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. The point at which CS
is pulled high after the conversion has been initiated determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance,
because the user does not have to worry about any power-up
times with the AD7475/AD7495 remaining fully powered all
the time. Figure 19 shows the general diagram of the AD7475/
AD7495 operating in this mode.
The conversion is initiated on the falling edge of CS , as
described in the Serial Interface section. To ensure the part
remains fully powered-up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS . If CS is brought high any time after the 10
edge, but before the 16
powered up but the conversion is terminated and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result. CS
SDATA
th
SCLK
SCLK
SCLK falling edge, the part remains
CS
CS
1
1
2
th
Figure 20. Entering Partial Power-Down Mode
SCLK falling
FOUR LEADING ZEROS + CONVERSION RESULT
Figure 19. Normal Mode
Rev. B | Page 16 of 24
may idle high until the next conversion or may idle low until
sometime prior to the next conversion (effectively idling CS
low).
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7475 is in partial
power-down, all analog circuitry is powered down except for
the bias current generator; and, in the case of the AD7495, all
analog circuitry is powered down except for the on-chip
reference and reference buffer.
To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the tenth falling edge of SCLK,
as shown in Figure 20. Once CS has been brought high in this
window of SCLKs, the part enters partial power-down, the
conversion that was initiated by the falling edge of CS is
terminated, and SDATA goes back into three-state. If CS is
brought high before the second SCLK falling edge, the part
remains in normal mode and does not power down. This avoids
accidental power-down due to glitches on the CS line.
QUIET
10
10
, has elapsed, by bringing CS low again.
16
16