AD7810YRZ Analog Devices Inc, AD7810YRZ Datasheet - Page 8

• Manufacturer Part Number: AD7810YRZ
• Description: IC ADC 10BIT SRL HS LP 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7810YRZ

• Data Interface: Serial
• Number Of Bits: 10
• Sampling Rate (per Second): 350k
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Resolution (bits): 10bit
• Sampling Rate: 350kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 3.5mA
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7810
POWER-UP TIMES
The AD7810 has a 1.5 µs power-up time. When V
connected, the AD7810 is in a low current mode of operation.
In order to carry out a conversion, the AD7810 must first be
powered up. The ADC is powered up by a rising edge on the
CONVST pin. A conversion is initiated on the falling edge of
CONVST. Figure 12 shows how to power up the AD7810 when
V
using the CONVST pin.
Care must be taken to ensure that the CONVST pin of the
AD7810 is logic low when V
POWER VS. THROUGHPUT RATE
By operating the AD7810 in Mode 2, the average power con-
sumption of the AD7810 decreases at lower throughput rates.
Figure 13 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power per-
formance for the AD7810. As the throughput rate is reduced, the
device remains in its power-down state longer and the average
power consumption over time drops accordingly.
For example, if the AD7810 is operated in a continuous sampling
mode with a throughput rate of 10 kSPS, the power consump-
tion is calculated as follows. The power dissipation during normal
operation is 9 mW, V
and the conversion time is 2.3 µs, the AD7810 can be said to
dissipate 9 mW for 3.8 µs (worst case) during each conversion
cycle. If the throughput rate is 10 kSPS, the cycle time is
100 µs and the average power dissipated during each cycle is
(3.8/100) × (9 mW) = 342 µW. Figure 2 shows a graph of
Power vs. Throughput.
CONVST
DD
CONVST
CONVST
is first connected or after the AD7810 is powered down
V
V
DD
DD
Figure 13. Automatic Power-Down
t
POWER-UP
t
t
1.5 s
POWER-UP
POWER-UP
Figure 12. Power-Up Times
1.5 s
1.5 s
DD
t
CONVERT
2.3 s
= 3 V. If the power-up time is 1.5 µs
100 s @ 10kSPS
MODE 1 (CONVST IDLES HIGH)
MODE 2 (CONVST IDLES LOW)
< 1 s
DD
t
CYCLE
is first applied.
POWER-DOWN
DD
is first
–8–
OPERATING MODES
Mode 1 Operation (High Speed Sampling)
When the AD7810 is used in this mode of operation, the part is
not powered down between conversions. This mode of opera-
tion allows high throughput rates to be achieved. The timing
diagram in Figure 14 shows how this optimum throughput rate
is achieved by bringing the CONVST signal high before the end
of the conversion. The AD7810 leaves its tracking mode and
goes into hold on the falling edge of CONVST. A conversion is
also initiated at this time. The conversion takes 2.3 µs to complete.
At this point, the result of the current conversion is latched into the
serial shift register, and the state of the CONVST signal checked.
The CONVST signal should be high at the end of the conversion
to prevent the part from powering down.
The serial port on the AD7810 is enabled on the rising edge of
the CONVST signal (see Serial Interface section). As explained
earlier, this rising edge should occur before the end of the con-
version process if the part is not to be powered down. A serial
read can take place at any stage after the rising edge of CONVST.
If a serial read is initiated before the end of the current con-
version process (i.e., at time “A”), the result of the previous
conversion is shifted out on the D
the serial read to extend beyond the end of a conversion. In this
case the new data will not be latched into the output shift regis-
ter until the read has finished. The dynamic performance of the
AD7810 typically degrades by up to 3 dBs while reading during
a conversion. If the user waits until the end of the conversion
process, i.e., 2.3 µs after falling edge of CONVST (Point “B”),
before initiating a read, the current conversion result is shifted out.
CONVST
SCLK
D
OUT
Figure 14. Mode 1 Operation Timing
t
2
A
t
1
B
OUT
CURRENT CONVERSION RESULT
pin. It is possible to allow
REV. B