LTC1277ISW Linear Technology, LTC1277ISW Datasheet - Page 8

• Manufacturer Part Number: LTC1277ISW
• Description: IC A/D CONV 12BIT W/SHTDN 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1277ISW

• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 20mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PI FU CTIO S
LTC1274/LTC1277
RD (Pin 20): Read Input. This enables the output drivers
when CS is low.
CS (Pin 21): The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 21): The BUSY output shows the converter
status. It is low when a conversion is in progress. The
rising Busy edge can be used to latch the conversion
result.
V
bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
this pin to analog ground to select unipolar operation.
V
tantalum in parallel with 0.1µF ceramic).
LTC1277
A
4.096V, unipolar (V
A
free of noise during conversion. For single-ended inputs
tie A
V
(10µF tantalum in parallel with 0.1µF ceramic). V
overdriven positive with an external reference voltage.
AGND (Pin 4): Analog Ground.
REFRDY (Pin 5): Reference Ready Signal. It goes high
when the reference has settled after SLEEP indicating that
the ADC is ready to sample.
SLEEP (Pin 6): SLEEP Mode Input. Tie this pin to low to put
the ADC in Sleep mode and save power (REFRDY will go
LOW). The device will draw 1µA in this mode.
NAP (Pin 7): NAP Mode Input. Pulling this pin low will shut
down all currents in the ADC except the reference. In this
mode the ADC draws 180µA. Wake-up from Nap mode is
about 620ns.
*The LTC1277 bipolar mode is in offset binary.
8
IN
SS
DD
IN
REF
U
+
–
(Pin 23): Negative 5V Supply. Negative 5V will select
(Pin 24): Positive 5V Supply. Bypass to AGND (10µF
IN
(Pin 2): Negative Analog Input. This pin needs to be
(Pin 1): Positive Analog Input. (A
(Pin 3): 2.42V Reference Output. Bypass to AGND
–
to analog ground.
U
SS
= 0V) or ±2.048V, bipolar (V
U
IN
+
– A
IN
–
REF
SS
) = 0V to
= –5V).
can be
D7 to D4* (Pins 8 to 11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11 to D0/8* (Pins 13 to 16): Three-State Data Outputs.
D11 is the Most Significant Bit.
V
allows a 5V or 3V logic interface with the processor. All
logic outputs (Data Bits, BUSY and REFRDY) will swing
between 0V and V
HBEN (Pin 18): High Byte Enable Input. The four Most
Significant Bits will appear at Pins 13 to 16 when this pin
is high. The LTC1277 uses straight binary for unipolar
mode and offset binary for bipolar mode.
CONVST (Pin 19): Conversion Start Signal. This active low
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be low).
RD (Pin 20): Read Input. This enables the output drivers
when CS is low.
CS (Pin 21): The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is low when a conversion is in progress.
V
bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
this pin to analog ground to select unipolar operation.
V
tantalum in parallel with 0.1µF ceramic).
Table 1. LTC1277 Two-Byte Read Data Bus Status
DATA
OUTPUTS
Low Byte
High Byte
LOGIC
SS
DD
(Pin 23): Negative 5V Supply. Negative 5V will select
(Pin 24): 5V Positive Supply. Bypass to AGND (10µF
(Pin 17): 5V or 3V Digital Power Supply. This pin
DB7
Low
D7
DB6
Low
D6
LOGIC
DB5
Low
D5
.
DB4
Low
D4
D3/11
DB11
DB3
D2/10
DB10
DB2
D1/9 D0/8
DB1
DB9
DB0
DB8