LTC1285IS8 Linear Technology, LTC1285IS8 Datasheet - Page 22

• Manufacturer Part Number: LTC1285IS8
• Description: IC A/D CONV SAMPLING 12BIT 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1285IS8

• Number Of Bits: 12
• Sampling Rate (per Second): 7.5k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 480µW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1285/LTC1288
TYPICAL APPLICATIONS
Interfacing to the Parallel Port of the INTEL 8051
Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1288 and parallel port micro-
processors. Normally the CS, CLK and D
be generated on 3 port lines and the D
a 4th port line. This works very well. However, we will
demonstrate here an interface with the D
LTC1288 tied together as described in the SERIAL INTER-
FACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1288 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
D
R2 B11 B10 B9
R3 B3 B2 B1 B0 0
22
CS
CLK
(
D IN
OUT
/D
DATA
ANALOG
OUT
INPUTS
FROM 1288 STORED IN 8501 RAM
MSB
LSB
)
AS IN INPUT AFTER THE 4TH RISING CLK
8051 P1.2 OUTPUTS DATA
LTC1288
AND BEFORE THE 4TH FALLING CLK
TO LTC1288
D
8051 P1.2 RECONFIGURED
CLK
B8 B7 B6 B5 B4
OUT
D
CS
IN
START
MUX ADDRESS
A/D RESULT
0
SGL/
DIFF
0
ODD/
U
SIGN
MSBF BIT LATCHED
INTO LTC1288
OUT
MSBF
IN
0
IN
N
P1.4
P1.3
P1.2
and D
signal read on
signals would
LTC1285/88 • TA01
8051
OUT
LTC1288 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
of the
B11
B10
LABEL
LOOP 1
LOOP 2
LOOP 3
LOOP 4
B9
B8
LTC1288 SENDS A/D RESULT
MNEMONIC
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
RRC
DJNZ
MOV
SETB
BACK TO 8051 P1.2
B7
B6
B5
A, #FFH
R4, #04
P1.2, C
P1.4
P1.4
A
P1.3
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
R4, LOOP 2
R2, A
A
R4, #04
C, P1.2
A
P1.3
P1.3
R4, LOOP 3
R4, #04
A
R4, LOOP 4
R3, A
P1.4
OPERAND
B4
B3
COMMENTS
D
Make sure CS is high
CS goes low
Load counter
Rotate D
SCLK goes low
Output D
SCLK goes high
Next bit
Bit 2 becomes an input
SCLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
SCLK goes low
Next bit
Store MSBs in R2
Clear Acc.
Load counter
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
SCLK goes low
Next bit
Load counter
Rotate right into Acc.
Next Rotate
Store LSBs in R3
CS goes high
IN
word for LTC1288
B2
IN
IN
B1
bit into Carry
bit to LTC1288
LTC1285/88 • TA07
B0