LTC1864CMS8 Linear Technology, LTC1864CMS8 Datasheet - Page 14

• Manufacturer Part Number: LTC1864CMS8
• Description: IC A/D CONV 1CH 16BIT 8-MSOP
• Manufacturer: Linear Technology

Specifications of LTC1864CMS8

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 400mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
LTC1864/LTC1865
LTC1865 OPERATION
Operating Sequence
The LTC1865 conversion cycle begins with the rising edge
of CONV. After a period equal to t
fi nished. If CONV is left high after this time, the LTC1865
goes into sleep mode drawing only leakage current. The
LTC1865’s 2-bit data word is clocked into the SDI input
on the rising edge of SCK after CONV goes low. Additional
inputs on the SDI pin are then ignored until the next CONV
cycle. The shift clock (SCK) synchronizes the data transfer
with each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex). After completing the data
transfer, if further SCK clocks are applied with CONV low,
SDO will output zeros indefi nitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
confi guration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
14
CONV
SDO
SCK
SDI
t
CONV
DON’T CARE
CONV
Hi-Z
, the conversion is
Figure 4. LTC1865 Operating Sequence
SLEEP MODE
single-ended mode, all input channels are measured
with respect to GND. A zero code will occur when the
“+” input minus the “–” input equals zero. Full scale oc-
curs when the “+” input minus the “–” input equals V
minus 1LSB. See Figure 5. Both the “+” and “–” inputs
are sampled at the same time so common mode noise
is rejected. The input span in the SO-8 package is fi xed
at V
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1865 SO-8 package is
internally tied to V
therefore equal to V
input of the LTC1865 MSOP package defi nes the span
of the A/D converter. The LTC1865 MSOP package can
operate with reference voltages from 1V to V
SINGLE-ENDED
DIFFERENTIAL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
S/D O/S
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
B15 B14
MUX MODE
MUX MODE
REF
1
2
= V
B13
3
B12
CC
4
B11
. If the “–” input in differential mode is
Table 1. Multiplexer Channel Selection
5
SGL/DIFF
B10
MUX ADDRESS
6
CC
1
1
0
0
CC
B9
. The span of the A/D converter is
7
. The voltage on the reference
B8
t
DON’T CARE
8
SMPL
ODD/SIGN
B7
9
B6
10
0
1
0
1
B5
11
B4
12
B3
13
CHANNEL #
0
+
+
–
B2
14
B1
15
B0*
16
1
+
–
+
CC
18645 F04
Hi-Z
.
GND
18645 TBL1
–
–
18645fb
REF