LTC2411CMS Linear Technology, LTC2411CMS Datasheet - Page 13

• Manufacturer Part Number: LTC2411CMS
• Description: IC A/D CONV 24BIT MICRPWR 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2411CMS

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2411/LTC2411-1 Status Bits
Input Range
V
0V V
–0.5 • V
V
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
IN
IN
< – 0.5 • V
0.5 • V
IN
REF
< 0.5 • V
Table 2. LTC2411/LTC2411-1 Output Data Format
Differential Input Voltage
V
V
0.5 • V
0.25 • V
0.25 • V
0
–1LSB
– 0.25 • V
– 0.25 • V
– 0.5 • V
V
*The differential input voltage V
**The differential reference voltage V
IN
IN
IN
REF
* 0.5 • V
* < –0.5 • V
*
V
REF
IN
REF
REF
< 0V
REF
REF
REF
REF
REF
** – 1LSB
SDO
SCK
**
** – 1LSB
CS
**
**
** – 1LSB
REF
REF
U
**
Hi-Z
**
SLEEP
U
BIT 31
EOC
1
IN
Bit 31 Bit 30 Bit 29 Bit 28
EOC
= IN
0
0
0
0
W
BIT 30
Bit 31
EOC
“0”
REF
0
0
0
0
0
0
0
0
0
0
+
– IN
= REF
2
DMY
0
0
0
0
–
.
+
Bit 30
DMY
BIT 29
– REF
SIG
0
0
0
0
0
0
0
0
0
0
Figure 3. Output Data Timing
U
SIG
3
1
1
0
0
–
.
Bit 29
BIT 28
MSB
MSB
SIG
1
1
1
1
1
0
0
0
0
0
1
0
1
0
4
DATA OUTPUT
BIT 27
Bit 28
MSB
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
1
0
0
0
0
1
1
1
1
0
5
Bit 27
0
1
1
0
0
1
1
0
0
1
26
LSB
Bit 26
BIT 5
LTC2411/LTC2411-1
0
1
0
1
0
1
0
1
0
1
24
27
BIT 0
Bit 25
0
1
0
1
0
1
0
1
0
1
32
CONVERSION
…
…
…
…
…
…
…
…
…
…
…
2411 F03
Bit 0
0
1
0
1
0
1
0
1
0
1
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