LTC2420IS8#TR Linear Technology, LTC2420IS8#TR Datasheet - Page 18

• Manufacturer Part Number: LTC2420IS8#TR
• Description: IC ADC 20BIT MICROPOWER 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC2420IS8#TR

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2420
into an internal static shift register. The device remains in
the sleep state until the first rising edge of SCK. Data is
shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
18
(INTERNAL)
SDO
SCK
CS
CONVERSION
Hi-Z
U
TEST EOC
U
SLEEP
Hi-Z
<t
EOCtest
BIT 23
EOC
Figure 9. Internal Serial Clock, Single Cycle Operation
W
BIT 22
–0.12V
REF
U
TO 1.12V
0.1V TO V
BIT 21
SIG
1 F
2.7V TO 5.5V
V
REF
V
REF
CC
IN
BIT 20
EXR
V
V
V
GND
CC
REF
IN
LTC2420
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
if the device is using its internal oscillator (F
or HIGH). If F
frequency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
BIT 19
MSB
SDO
SCK
DATA OUTPUT
CS
F
O
BIT 18
EOSC
V
O
EOCtest
CC
, then t
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
is driven by an external oscillator of
EOCtest
after EOC goes LOW (if CS is LOW
EOCtest
BIT 4
EOCtest
, the device remains in the sleep
is 3.6/f
after the falling edge of CS
EOCtest
V
CC
10k
EOSC
LSB
BIT 0
20
, the first rising
. If CS is pulled
EOCtest
0
= logic LOW
CONVERSION
Hi-Z
is 23 s
TEST EOC
2420 F09
Hi-Z