LTC1407CMSE-1 Linear Technology, LTC1407CMSE-1 Datasheet - Page 9

• Manufacturer Part Number: LTC1407CMSE-1
• Description: IC ADC 12BIT 3MSPS SAMPLE 10MSOP
• Manufacturer: Linear Technology

Specifications of LTC1407CMSE-1

• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 14mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TYPICAL PERFORMANCE CHARACTERISTICS
PIN FUNCTIONS
CH0
fully differentially with respect to CH0
1.25V differential swing with respect to CH0
V
CH0
differentially with respect to CH0
differential swing with respect to CH0
absolute input range.
V
a solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Can be
overdriven by an external reference voltage ≥ 2.55V and
≤V
CH1
fully differentially with respect to CH1
1.25V differential swing with respect to CH1
V
CH1
differentially with respect to CH1
differential swing with respect to CH1
absolute input range.
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
DD
REF
DD
DD
+
–
+
–
absolute input range.
absolute input range.
(Pin 3): 2.5V Internal Reference. Bypass to GND and
.
(Pin 2): Inverting Channel 0. CH0
(Pin 5): Inverting Channel 1. CH1
(Pin 1): Noninverting Channel 0. CH0
(Pin 4): Noninverting Channel 1. CH1
2.4902
2.4900
2.4898
2.4896
2.4894
2.4892
2.4890
2.6
Reference Voltage vs V
2.8
3.0
V
+
+
DD
, with a 1.25V to –1.25V
, with a 1.25V to –1.25V
3.2
(V)
–
–
, with a –1.25V to
, with a –1.25V to
+
+
DD
3.4
–
and a 0 to V
–
and a 0 to V
operates fully
operates fully
–
–
14071 G26
3.6
+
+
and a 0 to
and a 0 to
operates
operates
DD
DD
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
fl ow through these connections.
V
supplies 3V to the entire chip. Bypass to GND pin and
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in
mind that internal analog currents and digital output signal
currents fl ow through this pin. Care should be taken to
place the 0.1μF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each pair of
output data words represent the two analog input channels
at the start of the previous conversion. The output format
is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fi xed high or fi xed low state starts nap
mode. Four or more pulses with SCK in fi xed high or fi xed
low state starts sleep mode.
DD
2.4902
2.4900
2.4898
2.4896
2.4894
2.4892
2.4890
(Pin 7): 3V Positive Supply. This single power pin
0
Reference Voltage
vs Load Current
LTC1407-1/LTC1407A-1
0.2
V
0.4
DD
LOAD CURRENT (mA)
0.6
= 3V, T
0.8
1.0
A
= 25°C (LTC1407-1/LTC1407A-1)
1.2
1.4
1.6
1.8
14071 G27
2.0
14071fb
9