LTC2431IMS#TR Linear Technology, LTC2431IMS#TR Datasheet - Page 9

• Manufacturer Part Number: LTC2431IMS#TR
• Description: IC ADC 20BIT DIFFINPUT/REF10MSOP
• Manufacturer: Linear Technology

Specifications of LTC2431IMS#TR

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC2431IMSTR

GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and V
ground plane through a low impedance connection. All seven
pins must be connected to ground for proper operation.
V
a 10 F tantalum capacitor in parallel with 0.1 F ceramic
capacitor as close to the part as possible.
REF
The voltage on these pins can have any value between GND
and V
maintained more positive than the reference negative
input, REF
IN
voltage on these pins can have any value between
GND – 0.3V and V
converter bipolar input range (V
from – 0.5 • (V
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
(LTC2431)
V
(Pin 6) with a 10 F tantalum capacitor in parallel with
0.1 F ceramic capacitor as close to the part as possible.
REF
The voltage on these pins can have any value between GND
and V
maintained more positive than the reference negative
input, REF
IN
voltage on these pins can have any value between
GND – 0.3V and V
converter bipolar input range (V
PI FU CTIO S
CC
CC
+
+
U
(Pin 2): Positive Supply Voltage. Bypass to GND with
+
(Pin 5), IN
+
(Pin 4), IN
(Pin 1): Positive Supply Voltage. Bypass to GND
CC
(Pin 3), REF
CC
(Pin 2), REF
CC
decoupling. Connect each one of these pins to a
as long as the reference positive input, REF
as long as the reference positive input, REF
U
–
–
, by at least 0.1V.
, by at least 0.1V.
REF
–
–
) to 0.5 • (V
(Pin 6): Differential Analog Input. The
(Pin 5): Differential Analog Input. The
–
–
CC
(Pin 4): Differential Reference Input.
(Pin 3): Differential Reference Input.
U
CC
+ 0.3V. Within these limits, the
+ 0.3V. Within these limits the
(LTC2430)
REF
). Outside this input range
IN
IN
= IN
= IN
+
+
– IN
– IN
–
–
) extends
) extends
+
+
, is
, is
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
controls the ADC’s notch frequencies and conversion
time. When the F
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
to GND (F
and the digital filter first null is located at 60Hz. When F
is driven by an external clock signal with a frequency f
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
from – 0.5 • (V
range, the converter produces unique overrange and
underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
O
(Pin 14): Frequency Control Pin. Digital input that
O
= OV), the converter uses its internal oscillator
REF
O
pin is connected to V
) to 0.5 • (V
LTC2430/LTC2431
REF
CC
). Outside this input
) the SDO pin is in a
O
CC
pin is connected
(F
O
EOSC
= V
CC
/2560.
), the
EOSC
24301f
9
O
,