LTC1196-1ACS8 Linear Technology, LTC1196-1ACS8 Datasheet - Page 23

• Manufacturer Part Number: LTC1196-1ACS8
• Description: IC A/DCONV 8BIT 1MHZ SAMPL 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1196-1ACS8

• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS INFORMATION
3V VERSUS 5V PERFORMANCE COMPARISON
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of fi ve when the supply is reduced to 3V. The converter
slows down somewhat but still gives excellent performance
on a 3V rail. With a 3V supply, the LTC1196 converts in
1.6μs, samples at 450kHz, and provides a 500kHz linear-
input bandwidth.
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise fl oor is extremely
low, corresponding to a transition noise of less than 0.1LSB.
DC accuracy includes ±0.5LSB total unadjusted error at
5V. At 3V, linearity error is ±0.5LSB while total unadjusted
error increases to ±1LSB.
TYPICAL APPLICATIONS
PLD Interface Using the Altera EPM5064
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 12-bit counter and an equivalent
74HC595 8-bit shift register, as shown in Figure 12. The
circuit works as follows: bringing ENA HIGH makes the CS
output HIGH and the EN input LOW to reset the LTC1196
and disable the shift register. Bringing ENA LOW, the CS
DATA
CLK
ENA
Figure 12. An Equivalent Circuit of the EPM5064
CLK
ENA
CONVERTER
12-BIT
CS
SHIFT REGISTER
DATA
CLK
EN
8-BIT
B0-B7
1196/98 F12
B0-B7
CS
output goes HIGH for one CLK cycle with every 12 CLK
cycles. The inverted signal, EN, of the CS output makes
the 8-bit data available on the B0-B7 lines. Figures 13 and
14 show the interconnection between the LTC1196 and
EPM5064 and the timing diagram of the signals between
these two devices. The CLK frequency in this circuit can
run up to f
Table 1. 5V/3V Performance Comparison
LTC1196-1
P
Max f
Min t
INL (Max)
Typical ENOBs
Linear Input Bandwidth (ENOBs > 7)
LTC1198-1
P
P
Max f
Min t
INL (Max)
Typical ENOBs
Linear Input Bandwidth (ENOBs > 7)
DISS
DISS
DISS
Figure 13. Interfacing the LTC1196 to the Altera EMP5064 PLD
–
+
CONV
CONV
SMPL
SMPL
(Shutdown)
1
2
3
4
RESERVE PINS OF EPM5064:
2, 4-8,15-20, 22, 24, 26-30
+IN
–IN
GND
CS
CLK(MAX)
LTC1196
D
V
CLK
of the LTC1196.
V
OUT
REF
LTC1196/LTC1198
1μF
CC
8
7
6
5
V
CC
CLK
7.9 at 300kHz
7.9 at 300kHz
0.5LSB
750kHz
0.5LSB
50mW
50mW
600ns
600ns
1MHz
1MHz
15μW
1MHz
5V
31, 32, 43
33
23
34
35
9-13, 21,
ENA
CLK
DATA
3, 14, 25, 36
EPM5064
7.9 at 100kHz
7.9 at 100kHz
1196/98 F13
B7
B0
383kHz
500kHz
287kHz
500kHz
0.5LSB
0.5LSB
10mW
10mW
1.6μs
1.6μs
9μW
3V
23
1
37
38
39
40
41
42
44
119698fb