LTC2436-1IGN#TRPBF Linear Technology, LTC2436-1IGN#TRPBF Datasheet - Page 6

• Manufacturer Part Number: LTC2436-1IGN#TRPBF
• Description: IC CONV A/D 16B 2CH DIFF 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2436-1IGN#TRPBF

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI FU CTIO S
LTC2436-1
V
a 10 F tantalum capacitor in parallel with 0.1 F ceramic
capacitor as close to the part as possible.
REF
The voltage on these pins can have any value between GND
and V
maintained more positive than the reference negative
input, REF
CH0
CH0
CH1
CH1
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and V
the converter bipolar input range (V
from – 0.5 • (V
the converter produces unique overrange and underrange
output codes.
GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins
internally connected for optimum ground current flow and
V
plane through a low impedance connection. All five pins must
be connected to ground for proper operation.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
6
CC
CC
U
decoupling. Connect each one of these pins to a ground
(Pin 1): Positive Supply Voltage. Bypass to GND with
+
+
+
–
–
(Pin 2), REF
CC
(Pin 4): Positive Input for Differential Channel 0.
(Pin 6): Positive Input for Differential Channel 1.
(Pin 5): Negative Input for Differential Channel 0.
(Pin 7): Negative Input for Differential Channel 1.
as long as the reference positive input, REF
U
–
, by at least 0.1V.
REF
) to 0.5 • (V
–
U
(Pin 3): Differential Reference Input.
REF
). Outside this input range
CC
IN
. Within these limits
= IN
+
– IN
–
) extends
+
, is
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
controls the ADC’s notch frequencies and conversion
time. When the F
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When F
clock signal with a frequency f
signal as its system clock and the digital filter has 87dB
minimum rejection in the range f
110dB minimum rejection at f
O
(Pin 14): Frequency Control Pin. Digital input that
O
pin is connected to GND (F
EOSC
EOSC
O
is driven by an external
, the converter uses this
CC
EOSC
/2560 4%.
) the SDO pin is in a
/2560 14% and
O
= 0V), the
24361f