LTC2436-1CGN#TRPBF Linear Technology, LTC2436-1CGN#TRPBF Datasheet - Page 16
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LTC2436-1CGN#TRPBF
Manufacturer Part Number
LTC2436-1CGN#TRPBF
Description
IC CONV A/D 16B 2CH DIFF 16SSOP
Manufacturer
Linear Technology
Datasheet
1.LTC2436-1CGN.pdf
(28 pages)
Specifications of LTC2436-1CGN#TRPBF
Number Of Bits
16
Sampling Rate (per Second)
6.8
Data Interface
MICROWIRE™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
1mW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SSOP (0.150", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
APPLICATIO S I FOR ATIO
LTC2436-1
and the device begins outputting data at time t
the falling edge of CS (if EOC = 0) or t
LOW (if CS is LOW during the falling edge of EOC). The
value of t
oscillator (F
oscillator of frequency f
CS is pulled HIGH before time t
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle concludes
after the 19th rising edge. Data is shifted out the SDO pin
on each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 19th rising edge of SCK.
After the 19th rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
(INTERNAL)
16
SDO
SCK
CS
EOCtest
CONVERSION
Hi-Z
0
= logic LOW). If F
is 23 s if the device is using its internal
U
SLEEP
(OPTIONAL)
TEST EOC
EOSC
U
SLEEP
, then t
Hi-Z
<t
EOCtest
EOCtest
O
is driven by an external
BIT 18
EOC
EOCtest
W
Figure 9. Internal Serial Clock, Single Cycle Operation
EOCtest
EOCtest
, the device returns
CH0/CH1
ANALOG INPUT RANGE
, the first rising
BIT 17
–0.5V
after EOC goes
is 3.6/f
REF
EOCtest
U
TO 0.5V
0.1V TO V
REFERENCE
BIT 16
SIG
VOLTAGE
EOSC
1 F
2.7V TO 5.5V
REF
after
CC
. If
BIT 15
MSB
1
2
3
4
5
6
7
V
REF
REF
CH0
CH0
CH1
CH1
CC
LTC2436-1
+
–
+
–
+
–
BIT 14
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 19th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for aborting an invalid
conversion cycle, or synchronizing the start of a conver-
sion. If CS is pulled HIGH while the converter is driving
SCK LOW, the internal pull-up is not available to restore
SCK to a logic HIGH state. This will cause the device to exit
the internal serial clock mode on the next falling edge of
CS. This can be avoided by adding an external 10k pull-up
resistor to the SCK pin or by never pulling CS HIGH when
SCK is LOW.
Whenever SCK is LOW, the LTC2436-1’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a
LOW signal, the LTC2436-1’s internal pull-up remains
GND
SDO
SCK
DATA OUTPUT
CS
F
O
14
13
12
11
8, 9, 10, 15, 16
BIT 13
3-WIRE
SPI INTERFACE
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
BIT 2
BIT 1
V
CC
10k
BIT 0
LSB
CONVERSION
Hi-Z
TEST EOC
24361 F09
Hi-Z
24361f