MCP3202T-CI/SN Microchip Technology, MCP3202T-CI/SN Datasheet - Page 17
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MCP3202T-CI/SN
Manufacturer Part Number
MCP3202T-CI/SN
Description
IC ADC 12BIT 2.7V 2CH SPI 8-SOIC
Manufacturer
Microchip Technology
Datasheet
1.MCP3202-CISN.pdf
(32 pages)
Specifications of MCP3202T-CI/SN
Number Of Bits
12
Sampling Rate (per Second)
100k
Data Interface
Serial, SPI™
Number Of Converters
1
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP3202T-CI/SN
Manufacturer:
MICROCH
Quantity:
1 260
5.0
5.1
Communication with the MCP3202 is done using a
standard SPI-compatible serial interface. Initiating
communication with the device is done by bringing the
CS line low. See
up with the CS pin low, it must be brought high and
back low to initiate communication. The first clock
received with CS low and D
bit. The SGL/DIFF bit and the ODD/SIGN bit follow the
start bit and are used to select the input channel
configuration. The SGL/DIFF is used to select single
ended or psuedo-differential mode. The ODD/SIGN bit
selects which channel is used in single ended mode,
and is used to determine polarity in pseudo-differential
mode. Following the ODD/SIGN bit, the MSBF bit is
transmitted to and is used to enable the LSB first format
for the device. If the MSBF bit is high, then the data will
come from the device in MSB first format and any
further clocks with CS low will cause the device to
output zeros. If the MSBF bit is low, then the device will
output the converted word LSB first after the word
has been transmitted in the MSB first format.
See
for the MCP3202. The device will begin to sample the
analog input on the second rising edge of the clock,
after the start bit has been received. The sample period
will end on the falling edge of the third clock following
the start bit.
FIGURE 5-1:
© 2008 Microchip Technology Inc.
CS
CLK
D
D
Figure
IN
OUT
SERIAL COMMUNICATIONS
Overview
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely. See
** t
high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
5-2.
DATA
Table 5-1
: during this time, the bias current and the comparator power down while the reference input becomes a
Start
Figure
SGL/
DIFF
t
HI-Z
SUCS
Communication with the MCP3202 using MSB first format only.
5-1. If the device was powered
Figure 5-2
ODD/
SIGN BF
t
SAMPLE
shows the configuration bits
IN
MS
high will constitute a start
Null
Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
below for details on obtaining LSB first data.
t
CYC
t
CONV
Don’t Care
On the falling edge of the clock for the MSBF bit, the
device will output a low null bit. The next sequential
12 clocks will output the result of the conversion with
MSB first as shown in
from the device on the falling edge of the clock. If all
12 data bits have been transmitted and the device
continues to receive clocks while the CS is held low,
(and MSBF = 1), the device will output the conversion
result LSB first as shown in
are provided to the device while CS is still low (after the
LSB first data has been transmitted), the device will
clock out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the D
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 “Using the MCP3202 with Microcon-
troller (MCU) SPI Ports” for more details on using the
MCP3202 devices with hardware SPI ports.
TABLE 5-1:
Single Ended
Differential
Pseudo-
Mode
Mode
CONFIGURATION BITS FOR
THE MCP3202
SGL/
DIFF
t
t
CSH
DATA
1
1
0
0
Config
Figure
IN
Bits
**
line before the start bit. This is
ODD/
SIGN
0
1
0
1
Figure
Start
5-1. Data is always output
MCP3202
HI-Z
t
CYC
SGL/
DIFF
IN+
IN-
Selection
—
Channel
0
+
5-2. If more clocks
ODD/
SIGN
DS21034E-page 17
IN+
IN-
—
1
+
GND
-
-