MAX19507ETM+ Maxim Integrated Products, MAX19507ETM+ Datasheet - Page 24

• Manufacturer Part Number: MAX19507ETM+
• Description: IC ADC 8BIT 2CH 130MSPS 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19507ETM+

• Number Of Bits: 8
• Sampling Rate (per Second): 130M
• Data Interface: Serial, Parallel
• Number Of Converters: 2
• Power Dissipation (max): 171mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual-Channel, 8-Bit, 130Msps ADC
Figure 8. Simplified Clock Input Schematic
24
Figure 9. Dual-Bus Output Mode Timing
CLK+
CLK-
______________________________________________________________________________________
10kΩ
20kΩ
SAMPLE CLOCK
SELF-BIAS TURNED OFF FOR
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
AVDD
SINGLE-ENDED CLOCK
OR POWER-DOWN.
DATA, DOR
GND
5kΩ
5kΩ
DCLK
IN_
(PROGRAMMABLE)
50Ω
50Ω
TERMINATION
100Ω
n-10
SAMPLING
INSTANT
SAMPLE ON RISING EDGE
n
t
AD
t
DC
THRESHOLD
t
DD
SELECT
n-9
SAMPLING
INSTANT
n+1
2:1 MUX
t
HOLD
n-8
SAMPLING
INSTANT
DUAL-BUS OUTPUT MODE
t
n+2
CH
t
CLK
t
The input clock interface provides for flexibility in the
requirements of the clock driver. The MAX19507 accepts
a fully differential clock or single-ended logic-level clock.
For differential clock operation, connect a differential
clock to the CLK+ and CLK- inputs. In this mode, the
input common mode is established internally to allow for
AC-coupling. The differential clock signal can also be
DC-coupled if the common mode is constrained to the
specified 1V to 1.4V clock input common-mode range.
For single-ended operation, connect CLK- to GND and
drive the CLK+ input with a logic-level signal. When the
CLK- input is grounded (or pulled below the threshold of
the clock mode detection comparator) the differential-to-
single-ended conversion stage is disabled and the logic-
level inverter path is activated.
The MAX19507 offers a clock-divider option. Enable
clock division either by setting DIV0 and DIV1 through
the serial interface; see the Clock Divide/Data
SETUP
n-7
SAMPLING
INSTANT
n+3
n-6
t
CL
SAMPLING
INSTANT
n+4
n-5
SAMPLING
INSTANT
n+5
Clock Divider
n-4
Clock Inputs