MAX19506ETM+ Maxim Integrated Products, MAX19506ETM+ Datasheet - Page 15

• Manufacturer Part Number: MAX19506ETM+
• Description: IC ADC 8BIT 2CH 100MSPS 48TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19506ETM+

• Number Of Bits: 8
• Sampling Rate (per Second): 100M
• Data Interface: Serial, Parallel
• Number Of Converters: 2
• Power Dissipation (max): 139mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4. Simplified Reference Schematic
REFIO adjusts the reference potential, which, in turn,
adjusts the full-scale range of the ADC. Figure 4 shows
a simplified schematic of the reference system. An
internal bandgap voltage generator provides an internal
reference voltage. The bandgap potential is buffered
and applied to REFIO through a 10kΩ resistor. Bypass
REFIO with a 0.1µF capacitor to GND. The bandgap
voltage is applied to a scaling and level-shift circuit,
which creates internal reference potentials that estab-
lish the full-scale range of the ADC. Apply an external
voltage on REFIO to trim the ADC full scale. The allow-
able adjustment range is +5/-15%. The REFIO-to-ADC
gain transfer function is:
X = Don’t care.
Table 1. Parallel-Interface Pin Functionality
INTERNAL GAIN—BYPASS REFIO
EXTERNAL GAIN CONTROL—DRIVE REFIO
REFERENCE
BANDGAP
SPEN
0
1
1
1
1
1
1
1
1
1
V
BUFFER
FS
Reference Input/Output (REFIO)
1.250V
= 1.5 x [V
SDIN/FORMAT
______________________________________________________________________________________
Unconnected
AVDD
10kΩ
SDIN
X
X
X
X
X
X
REFIO
0
REFIO
LEVEL SHIFT
SCALE AND
/1.25] Volts
Dual-Channel, 8-Bit, 100Msps ADC
Unconnected
SCLK/DIV
0.1µF
EXTERNAL BYPASS
AVDD
SCLK
X
X
X
0
X
X
X
INTERNAL REFERENCE
(CONTROLS ADC GAIN)
Unconnected
CS/OUTSEL
AVDD
CS
X
X
X
X
X
X
0
Figure 5. Simplified Parallel-Interface Input Schematic
There are two ways to control the MAX19506 operating
modes. Full feature selection is available using the SPI
interface, while the parallel interface offers a limited set
of commonly used features. The programming mode is
selected using the SPEN input. Drive SPEN low for SPI
interface; drive SPEN high for parallel interface.
The parallel interface offers a pin-programmable inter-
face with a limited feature set. Connect SPEN to AVDD
to enable the parallel interface. See Table 1 for pin
functionality; see Figure 5 for a simplified parallel-inter-
face input schematic.
SCLK
SDIN
SPI interface active. Features are programmed through the
serial port (see the Serial Programming Interface section).
Two’s complement
Offset binary
Gray code
Clock divide-by-1
Clock divide-by-2
Clock divide-by-4
CMOS (dual bus)
MUX CMOS (channel A data bus)
MUX CMOS (channel B data bus)
CS
156kΩ
36kΩ
AVDD
Programming and Interface
29/32 AVDD
23/32 AVDD
3/32 AVDD
DESCRIPTION
Parallel Interface
DECODER
TO
CONTROL
LOGIC
15