CS5571-ISZ Cirrus Logic Inc, CS5571-ISZ Datasheet
CS5571-ISZ
Specifications of CS5571-ISZ
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CS5571-ISZ Summary of contents
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... AIN input and the VREF+ input. This significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. The CS5571 is a delta-sigma convert- er capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a low-laten- cy digital filter architecture ...
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... Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 Using the CS5571 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 34 8 ...
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... Figure 22. Noise Histogram, 4096 Samples Dither On, Input at Code Boundary . . . . . . . . . . . . . 24 Figure 23. Noise Histogram, 4096 Samples Dither Off, Input at Code Boundary . . . . . . . . . . . . . 24 Figure 24. CS5571 Digital Filter Response (DC to fs/ Figure 25. CS5571 Digital Filter Response ( kHz Figure 26. CS5571 Digital Filter Response (DC to 4fs Figure 27. Simple Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 28. More Complex Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 1. Output Coding, Two’ ...
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... Input 12 kHz, -0.5 dB Input 1 kHz, -0.5 dB Input -0.5 dB Input, 1 kHz -60 dB Input, 1 kHz (Note 4.096 ÷ 65536 = 62.5 µV. reset at power-up, at 25º C. CS5571 = 25°C. A Figure 6. Bipolar mode unless oth- Min Typ Max Unit ±%FS - 0.0008 ...
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... Unipolar Bipolar AIN Buffer On (BUFEN = V+) AIN Buffer Off (BUFEN = V-) ACOM (Note 7) VREF+ Buffer On (BUFEN = V+) VREF+ Buffer Off (BUFEN = V-) VREF Normal Operation Buffers On Buffers Off (Note 8) V1+ , V2+ Supplies V1-, V2- Supplies CS5571 Figure 6. Min Typ Max 0 to +VREF / 2 ±VREF / 600 - - 130 - - 130 - 4.2 2 ...
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... RDY falls at the end of conversion. 6 3/25/08 10:56 Symbol Min Internal Oscillator XIN External Clock f clk (Note 9) t res Internal Oscillator t wup External Clock t cpw (Note 10) t scn t scn t bus (Note 11) t buh CS5571 Typ Max Unit MHz 0.5 16 16.2 MHz µs - 120 - µs - 1536 - MCLKs 4 - ...
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... SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down resistors. 13. SCLK = MCLK/2. MCLK RDY SCLK(o) SDO MSB Figure 1. SSC Mode - Read Timing, CS remaining low (Not to Scale) DS768PP1 3/25/08 10:56 (CONTINUED) Symbol Min Pulse Width (low Pulse Width (high MSB–1 CS5571 Typ Max Unit -2 - MCLKs MCLKs t 5 LSB+1 LSB 7 ...
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... SCLK = MCLK/2. MCLK RDY SCLK( SDO MSB Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) 8 3/25/08 10:56 (CONTINUED) Symbol Min Pulse Width (low Pulse Width (high MSB–1 CS5571 Typ Max Unit MCLKs MCLKs - - LSB+1 LSB DS768PP1 ...
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... SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor. MCLK RDY SCLK( SDO MSB Figure 3. SEC Mode - Continuous SCLK Read Timing (Not to Scale) DS768PP1 3/25/08 10:56 (CONTINUED) Symbol - - (Note 16 CS5571 Min Typ Max Unit SCLK - LSB ns ...
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... Figure 4. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale) DIGITAL CHARACTERISTICS TMIN to TMAX 3.3V, ± 2.5V, ±5% or 1.8V, ±5%; VLR = 0V Parameter Input Leakage Current Digital Input Pin Capacitance Digital Output Pin Capacitance 10 3/25/08 10: MSB Symbol out CS5571 LSB Min Typ Max Unit - - 2 µ DS768PP1 ...
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... Minimum High-level Output Voltage: Maximum Low-level Output Voltage: DS768PP1 3/25/08 10:56 Guaranteed Limits Sym VL Min Typ 3.3 1.9 V 2.5 1.6 IH 1.8 1.2 3.3 V 2.5 IL 1.8 3.3 2.9 V 2.5 2.1 OH 1.8 1.65 3.3 V 2.5 OL 1.8 CS5571 Max Unit Conditions V 1.1 0. 0.36 0. 0.44 11 ...
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... V2+ V2- V1- V1+ V2- V2- (Note 18) VREF [VREF+] – [VREF-] Symbol [V1+] – [V1-] (Note 19 |V1-| ] (Note 20) - (Note 21 (AIN and VREF pins) V INA V IND T stg WARNING: CS5571 Min Typ Max 4.75 5.0 5.25 4.75 5.0 5. +2.375 +2.5 +2.625 +2.375 +2.5 +2.625 -2.375 -2.5 -2.625 -2.375 -2 ...
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... The converter can operate from an analog supply from ±2.5V. The digital interface supports stan- dard logic operating from 1.8, 2.5, or 3.3 V. The CS5571 may convert at rates up to 100 kSps when operating from a 16 MHz input clock. 3. THEORY OF OPERATION The CS5571 converter provides high-performance measurement signals. The converter can be used to perform single conversions or continuous conversions upon command ...
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... If the CS5571 is used to digitize AC signals, an external low-jitter clock source should be used. If the internal oscillator is used as the clock for the CS5571, the maximum conversion rate will be dictated by the oscillator frequency. If driven from an external MCLK source, the fast rise and fall times of the MCLK signal can result in clock coupling from the internal bond wire of the IC to the analog input ...
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... Voltage Reference The voltage reference for the CS5571 can range from 2.4 volt to 4.2 volts. A 4.096 volt reference is re- quired to achieve the specified signal-to-noise performance. tion of the voltage reference with either a single +5 V analog supply or with ±2.5 V. For optimum performance, the voltage reference device should be one that provides a capacitor connec- tion to provide a means of noise filtering, or the output should include some type of bandwidth-limiting fil- ter ...
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... Table 1. Output Coding, Two’s Complement Bipolar Input Voltage Complement >(VREF-1.5 LSB) VREF-1.5 LSB -0.5 LSB -VREF+0.5 LSB <(-VREF+0.5 LSB) Table 2. Output Coding, Offset Binary Unipolar Input Voltage >(VREF-1.5 LSB) VREF-1.5 LSB (VREF/2)-0.5 LSB +0.5 LSB <(+0.5 LSB) CS5571 Two’ Offset Binary ...
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... Typical Connection Diagrams The following figure depicts the CS5571 powered from bipolar analog supplies, +2.5 V and - 2.5 V. +2.048 -2.048 V +2.5 V +4.096 Voltage Reference (NOTE 1) -2.5 V Figure 6. CS5571 Configured Using ± 2.5V Analog Supplies DS768PP1 3/25/08 10:56 CS5571 49.9 AIN 150pF ...
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... The following figure depicts the CS5571 part powered from a single 5V analog supply and configured for unipolar measurement +2.048 V CS3003 / CS3004 +5 V +4.096 Voltage Reference (NOTE 1) Figure 7. CS5571 Configured for Unipolar Measurement Using a Single 5V Analog Supply 18 3/25/08 10:56 CS5571 49.9 AIN 150pF ...
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... The following figure depicts the CS5571 part powered from a single 5V analog supply and configured for bipolar measurement, referenced to a common mode voltage of 2.5 V. +4.548 V +2.5 V +0.452 V CS3003 / CS3004 Common Mode Voltage (2.5 V Typ.) CS3003 / CS3004 +5 V +4.096 Voltage Reference (NOTE 1) Figure 8. CS5571 Configured for Bipolar Measurement Using a Single 5V Analog Supply ...
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... AIN & VREF Sampling Structures The CS5571 uses on-chip buffers on the AIN and VREF+ inputs. Buffers provide much higher input im- pedance and therefore reduce the amount of drive current required from an external source. This helps minimize errors. The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is connected to the V1+ supply, the buffers will be enabled ...
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... Figures 11, 12, and 13 indicate the spectral performance of the CS5571 with and - 12 dB 5.55 kHz input signal. In each case, the captured data was windowed with a seven-term window function that exhibits 4 attenuation before being processed by the FFT. 0 -20 -40 -60 -80 -100 -120 -140 ...
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... Figures 14 and 15 illustrate the small signal performance of the CS5571 with a 5.55 kHz signal at -80 dB down. Figure 14 is with DITHER on and Figure 15 is with DITHER off. At -80 dB the signal is 1/10,000 of full scale, having a peak-to-peak magnitude of only a few codes. For small signals, DNL errors and quantization errors can introduce distortion because the error in the code size, or the quantization error without adequate dither, are a much greater percentage of the signal than with a full-scale input ...
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... Figure 19. Spectral Plot of Noise with Shorted Input DS768PP1 3/25/08 10: 10k 20k 30k Frequency (Hz) Figure 18. Spectral Performance, -116.3 dB Dither On 10 100 Frequency (Hz) CS5571 40k 50k Shorted Input 2M Samples @ 100 kSps 16 Averages 1k 10k 50k 23 ...
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... Figure 21. Noise Histogram, 4096 Samples 4500 4000 3500 3000 2500 2019 2000 1500 1000 500 Figure 23. Noise Histogram, 4096 Samples Dither Off, Input at Code Boundary CS5571 3940 Output (Codes) Dither Off, Code Center 2050 2046 Output (Codes) DS768PP1 ...
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... Figure 24. CS5571 Digital Filter Response (DC to fs/2) 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 Figure 25. CS5571 Digital Filter Response ( kHz) 0 -20 -40 -60 -80 -100 -120 Figure 26. CS5571 Digital Filter Response (DC to 4fs) DS768PP1 3/25/08 10:56 -0.0414 100 kSps -0 ...
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... Power Supplies & Grounding The CS5571 can be configured to operate with its analog supply operating from 5V, or with its analog sup- plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or 3.3V. ...
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... The analog input for the signal to be converted must remain active during the entire conversion until RDY falls. The CS5571 can be used in multiplexing applications, but the system timing for changing the multiplexer channel and for starting a new conversion will depend upon the multiplexer system architecture. ...
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... Select CH2 Convert on CH1 Figure 28. More Complex Multiplexing Scheme 28 3/25/08 10: 150pF 4700pF C0G 150pF 4700pF C0G 2k Select A2 Select A1 Select CH3 Select CH4 Convert on CH2 Convert on CH3 CS5571 CS5571 SW1 AIN ACOM Select A2 Select A1 Select CH1 Select CH2 Convert on CH4 Convert on CH1 DS768PP1 ...
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... In this configuration, the converters will convert syn- chronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge of MCLK. If CONV is held low continuously, reset (RST) can be used to synchronize multiple converters if RST is released on a falling edge of MCLK. DS768PP1 3/25/08 10:56 CS5571 29 ...
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... VREF+ DCR 10 15 VREF- CONV 11 14 BP/UP VLR2 12 13 DITHER RST CS5571 Ready Serial Clock Input/Output Serial Data Output Logic Interface Power Logic Interface Return Master Clock Negative Voltage 2 Positive Voltage 2 Digital Core Regulator Convert Logic Interface Return Reset DS768PP1 ...
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... SDO is the output pin for the serial output port. Data from this pin will be output at a rate deter- mined by SCLK and in a format determined by the BP/UP pin. Data is output MSB first and advances to the next data bit on the rising edges of SCLK. SDO will high impedance state when CS is high. DS768PP1 3/25/08 10:56 CS5571 31 ...
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... CS pin is inactive (high); or two master clock cycles before new data becomes available if the user holds CS low but has not started reading the data from the converter when in SEC mode. 32 3/25/08 10:56 CS5571 DS768PP1 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5571 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...
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... ORDERING INFORMATION Model Linearity CS5571-ISZ .0008% 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5571-ISZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision Date PP1 MAR 2008 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. ...