MAX11047ETN+ Maxim Integrated Products, MAX11047ETN+ Datasheet - Page 18

• Manufacturer Part Number: MAX11047ETN+
• Description: IC 16BIT PAR 250KSPS 56TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX11047ETN+

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Parallel
• Number Of Converters: 4
• Power Dissipation (max): 2.22W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN Exposed Pad
• Conversion Rate: 2000 KSPs
• Resolution: 16 bit
• Interface Type: Parallel
• Snr: 92.3 dB
• Voltage Reference: 3 V
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Power Dissipation: 3809.5 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Bypass AVDD and DVDD to the ground plane with
0.1µF ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10µF decoupling capacitor to
AVDD and DVDD per PCB. Interconnect all of the
AVDD inputs and DVDD inputs using two solid power
planes. For best performance, bring the AVDD power
plane in on the analog interface side of the devices and
the DVDD power plane from the digital interface side of
the devices.
Figure 4. Programming Configuration-Register Timing Requirements
Figure 5. Readout Timing Requirements
18
______________________________________________________________________________________
(USER SUPPLIED)
(USER SUPPLIED)
(USER SUPPLIED)
(USER SUPPLIED)
(USER SUPPLIED)
DB0–DB15
CR0–CR3
CS
RD
WR
CS
t
8
t
12
t
9
t
3
S
n
t
10
t
13
CONFIGURATION
t
4
REGISTER
t
11
For sampling periods near minimum (1µs) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to the
devices. This capacitor reduces the inductance seen by
the sampling circuitry and reduces the voltage transient
seen by the input source circuit.
t
6
t
7
t
5
S
n + 1