ADC14155CISQ/NOPB National Semiconductor, ADC14155CISQ/NOPB Datasheet - Page 17

• Manufacturer Part Number: ADC14155CISQ/NOPB
• Description: IC ADC 14BIT 155MSPS 1GHZ 48LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14155CISQ/NOPB

• Number Of Bits: 14
• Sampling Rate (per Second): 155M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 967mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14155CISQTR

3.0 DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK+, CLK−, PD
and CLK_SEL/DF.
3.1 Clock Inputs
The CLK+ and CLK− signals control the timing of the sampling
process. The CLK_SEL/DF pin (pin 8) allows the user to con-
figure the ADC for either differential or single-ended clock
mode (see Section 3.3). In differential clock mode, the two
clock signals should be exactly 180° out of phase from each
other and of the same amplitude. In the single-ended clock
mode, the clock signal should be routed to the CLK+ input and
the CLK− input should be tied to AGND in combination with
the correct setting from Table 3.
To achieve the optimum noise performance, the clock inputs
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
through a high speed buffer gate. This configuration is shown
in Figure 4. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90°. Figure 4 shows the recom-
mended clock input circuit.
The clock signal also drives an internal state machine. If the
clock is interrupted, or its frequency is too low, the charge on
the internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance.
It is highly desirable that the the source driving the ADC clock
pins only drive that pin. However, if that source is used to drive
other devices, then each driven pin should be AC terminated
with a series RC to ground, such that the resistor value is
equal to the characteristic impedance of the clock line and the
capacitor value is
where t
"L" is the line length and Z
of the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
board material. The units of "L" and t
(inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC14155 has a Duty Cycle Stabilizer. It is
designed to maintain performance over a clock duty cycle
range of 30% to 70%.
3.2 Power-Down (PD)
Power-down can be enabled through this two-state input pin.
Table 2 shows how to power-down the ADC14155.
V
V
RP
RN
= V
= V
PD
RM
RM
is the signal propagation rate down the clock line,
+ V
− V
PD
REF
REF
is about 150 ps/inch (60 ps/cm) on FR-4
/ 2
/ 2
O
is the characteristic impedance
PD
should be the same
17
The power-down mode allows the user to conserve power
when the converter is not being used. In the power-down state
all bias currents of the analog circuitry, excluding the refer-
ence are shut down which reduces the power consumption to
5 mW with no clock running. The output data pins are unde-
fined and the data in the pipeline is corrupted while in the
power-down mode.
The Power-down Mode Exit Cycle time is determined by the
value of the capacitors on the V
bypass pins (pins 43, 44 and 45) and is about 3 ms with the
recommended component values. These capacitors lose
their charge in the power-down mode and must be recharged
by on-chip circuitry before conversions can be accurate.
Smaller capacitor values allow slightly faster recovery from
the power down mode, but can result in a reduction in SNR,
SINAD and ENOB performance.
3.3 Clock Mode Select/Data Format (CLK_SEL/DF)
Single-ended versus differential clock mode and output data
format are selectable using this quad-state function pin. Table
3 shows how to select between the clock modes and the out-
put data formats.
4.0 DIGITAL OUTPUTS
Digital outputs consist of the 1.8V CMOS signals D0-D13,
DRDY and OVR.
The ADC14155 has 16 CMOS compatible data output pins:
14 data output bits corresponding to the converted input val-
ue, a data ready (DRDY) signal that should be used to capture
the output data and an over-range indicator (OVR) which is
set high when the sample amplitude exceeds the 14-bit con-
version range. Valid data is present at these outputs while the
PD pin is low.
Data should be captured and latched with the rising edge of
the DRDY signal. Depending on the setup and hold time re-
quirements of the receiving circuit (ASIC), either the rising
edge or the falling edge of the DRDY signal can be used to
latch the data. Generally, rising-edge capture would maxi-
mize setup time with minimal hold time; while falling-edge-
capture would maximize hold time with minimal setup time.
However, actual timing for the falling-edge case depends
greatly on the CLK frequency and both cases also depend on
the delays inside the ASIC. Refer to the AC Electrical Char-
acterisitics table.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
TABLE 3. Clock Mode and Data Format Selection Table
Input Voltage
CLK_SEL/DF
(2/3) * V
(1/3) * V
AGND
TABLE 2. Power Down Selection Table
V
DR
A
PD Input Voltage
and DRGND. These large charging current
A
A
AGND
V
A
Single-Ended
Single-Ended
Clock Mode
Differential
Differential
RP
Power State
Power-down
, V
RM
On
and V
2's Complement
2's Complement
Offset Binary
Offset Binary
Output Data
Format
RN
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