KAD2710L-27Q68 Intersil, KAD2710L-27Q68 Datasheet - Page 14

• Manufacturer Part Number: KAD2710L-27Q68
• Description: IC ADC 10BIT 275MSPS SGL 68-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD2710L-27Q68

• Number Of Bits: 10
• Sampling Rate (per Second): 275M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 314mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• For Use With: KDC2710LEVAL - DAUGHTER CARD FOR KAD2710
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INP
INN
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1.
Any internal aperture jitter combines with the input clock jitter
in a root-sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
Equivalent Circuits
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
AVDD3
AVDD3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
FIGURE 28. ANALOG INPUTS
2pF
2pF
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Φ
F 1
Φ
F 1
14
Φ
F 2
Φ
F 2
DATA
DATA
Csamp
Csamp
0.3pF
0.3pF
FIGURE 30. LVDS OUTPUTS
OVDD
Pipeline
Pipeline
Charge
Charge
To
To
KAD2710L
DATA
DATA
OVDD
Digital Outputs
Data is output on a parallel bus with LVDS-compatible
drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
CLKN
CLKP
OVDD
AVDD (or unconnected)
AVDD2
AVDD2
D[9:0]P,
ORP
D[9:0]N,
ORN
2SC PIN
AVSS
TABLE 3. 2SC PIN SETTINGS
FIGURE 29. CLOCK INPUTS
Two’s Complement
AVDD2
MODE
Binary
December 5, 2008
Generation
To Clock
FN6818.0