AD7980BRMZ Analog Devices Inc, AD7980BRMZ Datasheet - Page 17

• Manufacturer Part Number: AD7980BRMZ
• Description: ADC 16BIT 1MSPS 1.25LSB 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7980BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 10mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Supply Current: 350pA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 3-WIRE, WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 31, and the corresponding timing is given in
Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7980 enters the acquisition phase and powers down.
SDI=1
CNV
AQUISITION
SCK
SDO
CONVERSION
Figure 32. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
t
CONV
t
CNVH
t
EN
D15
1
t
HSDO
Rev. B | Page 17 of 28
D14
t
2
CYC
AQUISITION
D13
t
3
ACQ
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate provided that it has
an acceptable hold time. After the 16th SCK falling edge or
when CNV goes high, whichever is earlier, SDO returns to high
impedance.
t
DSDO
t
SCKL
14
VIO
t
SCKH
Figure 31. 3-Wire CS Mode Without Busy Indicator
SDI
t
SCK
15
D1
AD7980
Connection Diagram (SDI High)
CNV
SCK
16
D0
SDO
t
DIS
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7980