CS5368-CQZ Cirrus Logic Inc, CS5368-CQZ Datasheet - Page 32

• Manufacturer Part Number: CS5368-CQZ
• Description: IC ADC 8CH 114DB 216KHZ 48-LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5368-CQZ

• Package / Case: 48-LQFP
• Number Of Converters: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Power Dissipation (max): 1.12W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 8
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 680 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1157 - BOARD EVAL FOR CS5368 192KHZ ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1090

32
5. REGISTER MAP
In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All
registers above 0Ah are RESERVED.
5.1
5.2
5.3
Adr
00
01
02
03
04
05
06
07
08
09
0A
R/W
R/W
R/W
RESERVED
RESERVED
RESERVED
R
Name
Register Quick Reference
OVFM
00h (REVI) Chip ID Code & Revision Register
Default: See description
The Chip ID Code & Revision Register is used to store the ID and revision of the chip.
Bits[7:4] contain the chip ID, where the CS5368 is represented with a value of 0x8.
Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented
as 0x1, etc.
01h (GCTL) Global Mode Control Register
Default: 0x00
The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data
format and the Master clock dividers for all channels. It also contains a Control Port enable bit.
Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone
Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding reg-
ister values become functional.
Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit in-
vokes 256X mode (divide XTI by 1.0 - pass through).
PDNE
MUTE
SDEN
GCTL
OVFL
REVI
HPF
CP-EN
7
7
OVFM8
MUTE8
CP-EN
OVFL8
HPF8
7
-
-
-
RESERVED
CLKMODE
CLKMODE
6
6
OVFM7
MUTE7
CHIP-ID[3:0]
OVFL7
HPF7
6
-
-
-
CHIP-ID[3:0]
RESERVED
PDN-BG
5
5
OVFM6
MUTE6
OVFL6
HPF6
MDIV[1:0]
5
-
-
-
MDIV[1:0]
PDN-OSC
OVFM5
4
4
MUTE5
OVFL5
HPF5
4
-
-
-
OVFM4
MUTE4
SDEN4
OVFL4
PDN87
3
3
HPF4
3
-
-
-
DIF[1:0]
DIF[1:0]
OVFM3
MUTE3
SDEN3
OVFL3
PDN65
2
REVISION[3:0]
2
HPF3
REVISION[3:0]
2
-
-
-
OVFM2
MUTE2
PDN43
SDEN2
OVFL2
HPF2
1
1
1
-
-
-
MODE[1:0]
MODE[1:0]
CS5368
DS624F4
OVFM1
MUTE1
SDEN1
OVFL1
PDN21
HPF1
0
0
0
-
-
-