CS5529-ASZ Cirrus Logic Inc, CS5529-ASZ Datasheet - Page 11

• Manufacturer Part Number: CS5529-ASZ
• Description: IC ADC 16BIT W/6BIT LATCH 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5529-ASZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 16
• Data Interface: Serial
• Power Dissipation (max): 3.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 101 SPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 8 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1015 - EVAL BOARD FOR CS5529
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1110-5

ages. The differential voltage between VREF+ and
VREF- sets the nominal full scale input span of the
converter. For a single-ended reference voltage,
such as the LT1019-2.5, the reference output is
connected to the VREF+ pin of the CS5529 and the
ground reference for the LT1019-2.5 is connected
to the VREF- pin.
Serial Port
The CS5529 includes a microcontroller with a
command register, a configuration register, a con-
version data register (read only), and a gain and off-
set register for calibration. All registers, except the
8-bit command register, are 24-bits in length. Fig-
DS246F5
V ≤ 25mV
i = fV C
n
os
Figure 1. Input models for AIN+ and AIN- pins.
AIN
os
Offset Register (1 × 24)
f = 32.768 kHz
φ Coarse
1
φ Fine
C = 20pF
1
Latch Outputs
Low Power Mode
Output Word Rates
Unipolar/Bipolar
Reset System
etc.
Configuration Register (1 × 24)
Gain Register (1 × 24)
Figure 3. CS5529 Register Diagram.
ure 3 illustrates a block diagram of all the internal
register.
After a system initialization or reset, the serial port
is set to the command mode. The converter stays in
this mode until a valid 8-bit command is received
(the first 8-bits into the serial port). Once a valid 8-
bit command is received and interpreted by the
ADC’s command register, the serial port enters the
data mode. In data mode the next 24 serial clock
pulses shift data either into or out of the serial port
(72 serial clock pulses are needed if the setup reg-
ister command is issued). The Command Register
Descriptions section illustrates all valid com-
mands.
V ≤ 25mV
i = fV C
n
Figure 2. Input model for VREF+ and VREF- pins.
os
VREF
os
Command Register (1 × 8)
f = 32.768 kHz
Conversion Data Register (1x24)
Interface
Serial
φ Coarse
2
φ Fine
C = 10pF
1
CS5529
CS
SDI
SDO
SCLK
11