CS5340-CZZ Cirrus Logic Inc, CS5340-CZZ Datasheet - Page 17

• Manufacturer Part Number: CS5340-CZZ
• Description: IC ADC AUD 101DB 200KHZ 16-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5340-CZZ

• Package / Case: 16-TSSOP
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 3.3 V or 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 90 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 3.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1544 - BOARD EVAL FOR CS5340 STEREO ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1081-5

DS601F2
4.2.3
4.3
MCLK/LRCK Ratio
* Quad Speed, 64x only available in Master Mode.
S D A T A
S D A T A
LR C K
S C L K
LR C K
S C LK
Serial Audio Interface
The CS5340 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5340 will detect
the logic level on SDOUT (pin 4). A 10 kΩ pull-up to VL is needed to select I²S format, and a 10 kΩ pull-
down to GND is needed to select Left-Justified format.
audio formats. Please see
serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audio
interface formats.
Master Clock
The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the speed mode and
frequency of the MCLK.
Table 4
that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x
for Single-, Double-, and Quad-Speed Modes, respectively).
2 3 2 2
2 3 2 2
lists some common audio output sample rates and the required MCLK frequency. Please note
9
9
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
8
8
7
7
6
6
5
5
L e ft C h a n n e l
4
4
L e ft C h an n e l
3
Single-Speed Mode
3
SAMPLE RATE (kHz)
Figure 20. Left-Justified Serial Audio Interface
2
2
Figures 13
Table 3
1
1
256x, 512x
0
Table 3. Master Clock (MCLK) Ratios
0
Figure 19. I²S Serial Audio Interface
44.1
88.2
192
shows a listing of the external MCLK/LRCK ratios that are required.
32
48
64
96
Confidential Draft
through 16, for more information on the required timing for the two
3/11/08
2 3 2 2
2 3 2 2
Double-Speed Mode
Figures 19
MCLK (MHz)
128x, 256x
22.5792
22.5792
11.2896
11.2896
9
12.288
24.576
12.288
24.576
12.288
24.576
9
8.192
8.192
8
8
7
7
6
6
and
5
5
R ig h t C h a n n e l
4
R ig h t C h a n n e l
4
20
3
3
illustrate the I²S and Left-Justified
2
2
1
1
0
0
Quad-Speed Mode
64x*,128x
CS5340
23 2 2
2 3 2 2
17