AD7994BRUZ-0 Analog Devices Inc, AD7994BRUZ-0 Datasheet - Page 21

• Manufacturer Part Number: AD7994BRUZ-0
• Description: IC ADC 12BIT 4CHAN I2C 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7994BRUZ-0

• Data Interface: I²C, Serial
• Number Of Bits: 12
• Sampling Rate (per Second): 188k
• Number Of Converters: 1
• Power Dissipation (max): 2.2mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 188kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 1.4mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7994CBZ - BOARD EVALUATION FOR AD7994CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Hysteresis Register (CH1/CH2/CH3/CH4)
Each hysteresis register is a 16-bit read/write register, of which
only the 12 LSBs of the register are used. The hysteresis register
stores the hysteresis value, N, when using the limit registers.
Each pair of limit registers has a dedicated hysteresis register.
The hysteresis value determines the reset point for the ALERT
pin/Alert_Flag if a violation of the limits has occurred. For
example, if a hysteresis value of 8 LSB is required on the upper
and lower limits of Channel 1, the 12-bit word, 0000 0000 0000
1000, should be written to the hysteresis register of CH1, the
address of which is shown in Table 8. On power-up, the
hysteresis registers contain a value of 8 LSB for the AD7994 and
2 LSB for the AD7993. If a different hysteresis value is required,
that value must be written to the hysteresis register for the
channel in question. For the AD7993, D1 and D0 of the
hysteresis register should contain 0s.
Table 20. Hysteresis Register (First Read/Write)
D15
0
Table 21. Hysteresis Register (Second Read/Write)
D7
B7
Using the Limit Registers to Store Min/Max Conversion
Results for CH1 to CH4
If full scale, that is, all 1s, is written to the hysteresis register for
a particular channel, the DATA
that channel no longer act as limit registers as previously
described, but instead act as storage registers for the maximum
and minimum conversion results returned from conversions on
a channel over any given period of time. This function is useful
in applications where the widest span of actual conversion
results is required rather than using the alert to signal that an
intervention is necessary. This function could be useful for
monitoring temperature extremes during refrigerated goods
transportation.
It must be noted that on power-up, the contents of the
DATA
contents of the DATA
Therefore, minimum and maximum conversion values being
stored in this way are lost if power is removed or cycled.
HIGH
D14
0
D6
B6
register for each channel are full scale, while the
D13
0
D5
B5
LOW
D12
0
D4
B4
registers are zero scale by default.
HIGH
D11
B11
D3
B3
and DATA
D10
B10
D2
B2
LOW
registers for
D9
B9
D1
B1
D8
B8
D0
B0
Rev. 0 | Page 21 of 32
ALERT STATUS REGISTER
The alert status register is an 8-bit read/write register that
provides information on an alert event. If a conversion results in
activating the ALERT pin or the Alert_Flag bit in the
conversion result register, as described in the Limit Registers
section, the alert status register may be read to gain further
information. It contains two status bits per channel, one
corresponding to the DATA
DATA
violation occurred—that is, on which channel—and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on the other channel between receiving the
first alert and interrogating the alert status register, the
corresponding bit for that alert event is also set.
The entire contents of the alert status register may be cleared by
writing 1, 1 to Bits D2 and D1 in the configuration register, as
shown in Table 12. This may also be achieved by writing all 1s
to the alert status register itself. Therefore, if the alert status
register is addressed for a write operation, which is all 1s, the
contents of the alert status register are cleared or reset to all 0s.
Table 22. Alert Status Register
D7
CH4
Table 23. Alert Status Register Bit Function Descriptions
Bit
D0
D1
D2
D3
D4
D5
D6
D7
HI
Mnemonic
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
LOW
D6
CH4
LO
HI
LO
HI
LO
HI
LO
HI
limit. The bit with a status of 1 shows where the
LO
D5
CH3
Comment
Violation of DATA
this bit set to 1, no violation if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
Violation of DATA
this bit set to 1, no violation if if bit is set to 0.
HI
D4
CH3
HIGH
LO
limit and the other to the
D3
CH2
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HI
AD7993/AD7994
limit on Channel 1 if
limit on Channel 2 if
limit on Channel 3 if
limit on Channel 4 if
limit on Channel 1 if
limit on Channel 2 if
limit on Channel 3 if
limit on Channel 4 if
D2
CH2
LO
D1
CH1
HI
D0
CH1
LO