CS5513-BSZ Cirrus Logic Inc, CS5513-BSZ Datasheet - Page 19

• Manufacturer Part Number: CS5513-BSZ
• Description: IC ADC 20BIT INTERNAL OSC 8SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5513-BSZ

• Data Interface: Serial
• Number Of Bits: 20
• Sampling Rate (per Second): 326
• Number Of Converters: 1
• Power Dissipation (max): 2.7mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Resolution (bits): 20bit
• Sampling Rate: 100SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 385µA
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1707

valid conversion due to the modified Sinc
characteristics.
2.5.5
The settling performance of the CS5510/11/12/13
in multiplexed applications is determined by the
Sinc
conversion cycles after the analog input has
switched. In this case, the throughput is reduced
by a factor of four as the first three conversions af-
ter the step is applied will not be fully settled.
If the application does not require the maximum
throughput possible from the ADC, the multiplexer
can be switched at any time. In this case, the sys-
tem must wait for at least five conversion cycles for
a fully-settled result from the ADC.
DS337F4
Frequency
4
(Hz)
38
39
40
41
42
43
44
45
46
filter. To settle, a step input requires 4 full
Multiplexed Applications
Rejection
(dB)
37
39
42
46
49
54
58
64
72
Frequency
-100
-120
-140
-20
-40
-60
-80
0
Table 4. Digital Filter Response at 32.768 kHz.
(Hz)
0
47
48
49
50
51
52
53
54
55
Figure 20. Digital Filter Response.
20
Rejection
(dB)
105
84
92
88
92
89
86
85
87
47 Hz
4
filter
40
Frequency (Hz)
Frequency
60
If maximum throughput is required in a multiplexed
application, the multiplexer must be switched at the
correct time during the data collection process. For
maximum throughput with the CS5510/12, switch-
ing of a multiplexer should occur 595 SCLK cycles
after SDO falls. For maximum throughput with the
CS5511/13, switching of a multiplexer should oc-
cur on the rising edge of SDO during a conversion
in which the data word is not read. The conversion
data that is immediately available when SDO falls
again is valid, and represents the analog input from
the previous multiplexer setting. The next three
conversions from the part will be unsettled values,
and the fourth conversion will represent a fully-set-
tled result from the new multiplexer setting. The
multiplexer should be switched again at the appro-
(Hz)
56
57
58
59
60
61
62
63
64
63 Hz
CS5510/12
SCLK = 32.768 kHz
80
Rejection
(dB)
109
104
91
94
89
88
92
84
77
100
Frequency
120
CS5510/11/12/13
(Hz)
65
66
67
68
69
70
71
-
-
Rejection
(dB)
73
69
66
64
63
61
60
-
-
19