AD7904BRUZ Analog Devices Inc, AD7904BRUZ Datasheet - Page 22

• Manufacturer Part Number: AD7904BRUZ
• Description: IC ADC 8BIT 4CH 1MSPS 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7904BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 13.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 8bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 2.7mA
• Digital Ic Case Style: TSSOP
• Package: 16TSSOP
• Resolution: 8 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 4
• Digital Interface Type: Serial (SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 49(Min) dB
• Polarity Of Input Voltage: Unipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD79X4CBZ - BOARD EVALUATION FOR AD79X4CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7904/AD7914/AD7924
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7904/AD7914/AD7924.
For the AD7904/AD7914/AD7924 the 8/10/12 bits of data are
preceded by two leading zeros and two channel address bits ADD1
and ADD0, identifying which channel the result corresponds to.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP on the first falling edge of SCLK.
The first falling edge of SCLK will also clock out the second
leading zero to be read in by the microcontroller or DSP on the
second SCLK falling edge, and so on. The remaining two address
bits and 8/10/12 data bits are then clocked out by subsequent
SCLK falling edges beginning with the first address bit ADD1;
thus the second falling clock edge on the serial clock has the
second leading zero provided and also clocks out address bit
ADD1. The final bit in the data transfer is valid on the sixteenth falling
edge, having been clocked out on the previous (fifteenth) falling edge.
Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, i.e., the WRITE bit, has been set to 1.
The AD7904 will output two leading zeros, two channel address
bits that the conversion result corresponds to, followed by the 8-bit
conversion result, and four trailing zeros. The AD7914 will
output two leading zeros, two channel address bits that the
conversion result corresponds to, followed by the 10-bit conver-
sion result, and two trailing zeros. The 16-bit word read from
the AD7924 will always contain two leading zeros, two channel
address bits that the conversion result corresponds to, followed
by the 12-bit conversion result.
MICROPROCESSOR INTERFACING
The serial interface on the AD7904/AD7914/AD7924 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7904/AD7914/AD7924 with some of the more common
microcontroller and DSP serial interface protocols.
AD7904/AD7914/AD7924 to TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7904/AD7914/AD7924. The CS input allows easy inter-
facing between the TMS320C541 and the AD7904/AD7914/
AD7924 without any glue logic required. The serial port of
the TMS320C541 is set up to operate in burst mode with
internal CLKX0 (TX serial clock on serial port 0) and FSX0
(TX frame sync from serial port 0). The serial port control
register (SPC) must have the following setup: FO = 0, FSM
= 1, MCM = 1, and TXM = 1. The connection diagram is
shown in Figure 19. It should be noted that for signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C541 provides equidistant sampling.
The V
same supply voltage as that of the TMS320C541. This allows
the ADC to operate at a higher voltage than the serial inter-
face, i.e., TMS320C541, if necessary.
DRIVE
pin of the AD7904/AD7914/AD7924 takes the
–22–
AD7904/AD7914/AD7924 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7904/AD7914/AD7924 without any glue logic required. The
V
supply voltage as that of the ADSP-218x. This allows the
ADC to operate at a higher voltage than the serial interface,
i.e., ADSP-218x, if necessary.
The SPORT0 control register should be set up as follows:
The connection diagram is shown in Figure 20. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
Alternate Framing Mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC, and under certain conditions equidistant sampling may
not be achieved.
The Timer register, and so on, are loaded with a value that
will provide an interrupt at the required sample interval. When
an interrupt is received, a value is transmitted with TFS/DT
(ADC control word). The TFS is used to control the RFS and
thus the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low, and
High before transmission will start. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master
cycle time would be 25 ns. If the SCLKDIV register is loaded with
the value 3, then a SCLK of 5 MHz is obtained and eight master
clock periods will elapse for every one SCLK period. Depending
on the throughput rate selected, if the timer register was loaded
with the value, say 803 (803 + 1 = 804), then 100.5 SCLKs will
occur between interrupts and subsequently between transmit
DRIVE
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7924
AD7904/
AD7914/
pin of the AD7904/AD7914/AD7924 takes the same
Figure 19. Interfacing to the TMS320C541
DOUT
SCLK
V
*
DRIVE
DIN
CS
CLKX
CLKR
DR
DT
FSX
FSR
TMS320C541*
V
DD
REV. 0