LTC1286CS8#PBF Linear Technology, LTC1286CS8#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC1286CS8#PBF
• Description: IC A/D CONV SAMPLING 12BIT 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1286CS8#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 12.5k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATION INFORMATION
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1286/LTC1298 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The V
a 10 F tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1286/LTC1298 can
also operate with smaller 1 F or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
CC
pin should be bypassed to the ground plane with
"+" INPUT
"–" INPUT
D
CLK
OUT
D
CS
IN
U
U
Figure 7. LTC1298 “+” and “–” Input Settling Windows
W
START
U
SGL/DIFF
SAMPLE-AND-HOLD
Both the LTC1286 and the LTC1298 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1286 acquires input signals from “+” input
relative to “–” input during the t
However, the S&H of the LTC1298 can sample input
signals in the single-ended mode or in the differential
inputs during the t
Single-Ended Inputs
The sample-and-hold of the LTC1298 allows conversion
of rapidly varying signals. The input voltage is sampled
during the t
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
1ST BIT TEST "–" INPUT MUST
SAMPLE
SETTLE DURING THIS TIME
SETTLE DURING
"+" INPUT MUST
THIS TIME
t
SMPL
SMPL
MSBF
time as shown in Figure 7. The sampling
SMPL
HOLD
time (see Figure 7).
LTC1286/LTC1298
t
CONV
DON'T CARE
SMPL
LTC1096/8 • F07
B11
time (see Figure 1).
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