MCP3001-I/SN Microchip Technology, MCP3001-I/SN Datasheet - Page 16

• Manufacturer Part Number: MCP3001-I/SN
• Description: IC ADC 10BIT 2.7V 1CH SPI 8-SOIC
• Manufacturer: Microchip Technology

Specifications of MCP3001-I/SN

• Data Interface: Serial, SPI™
• Number Of Bits: 10
• Sampling Rate (per Second): 200k
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Resolution (bits): 10bit
• Sampling Rate: 200kSPS
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 400µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3001
6.0
6.1
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3001. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3001 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3001 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3001. Figure 6-1 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the ADC on the fall-
ing edge of the third clock pulse. After the first eight
clocks have been sent to the device, the microcontrol-
FIGURE 6-1:
FIGURE 6-2:
DS21293C-page 16
D
D
CLK
CLK
CS
CS
OUT
OUT
APPLICATIONS INFORMATION
Using the MCP3001 with
Microcontroller SPI Ports
HI-Z
HI-Z
SPI Communication with the MCP3001 using 8-bit segments (Mode 0,0: SCLK idles low).
SPI Communication with the MCP3001 using 8-bit segments (Mode 1,1: SCLK idles high).
?
?
1
1
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of first 8 bits
?
?
2
2
NULL
NULL
BIT
BIT B9
0
0
3
3
B9
B9
B9
4
4
B8
B8
B8
B8
5
5
B7
B7
B7
B7
6
6
B6
B6
B6
B6
7
7
B5
B5
B5
8
B5
8
B4
B4
B4
B4
Data stored into MCU receive register
after transmission of second 8 bits
9
Data stored into MCU receive register
after transmission of second 8 bits
9
B3
B3
B3 B2
B3
10
10
B2
B2
B2
11
11
B1
B1
B1
B1
12
12
ler’s receive buffer will contain two unknown bits (the
output is at high impedance for the first two clocks), the
null bit and the highest order five bits of the conversion.
After the second eight clocks have been sent to the
device, the MCU receive register will contain the lowest
order five bits and the B1-B4 bits repeated as the ADC
has begun to shift out LSB first data with the extra
clocks. Typical procedure would then call for the lower
order byte of data to be shifted right by three bits to
remove the extra B1-B4 bits. The B9-B5 bits are then
rotated 3 bits to the right with B7-B5 rotating from the
high order byte to the lower order byte. Easier manipu-
lation of the converted data can be obtained by using
this method.
Figure 6-2 shows SPI Mode 1,1 communication which
requires that the clock idles in the high state. As with
mode 0,0, the ADC outputs data on the falling edge of
the clock and the MCU latches data from the ADC in on
the rising edge of the clock.
B0
B0
B0
B0
13
13
B1
B1
B1
B1
14
14
B2
B2
B2
B2
15
15
B3
B3
16
B3
16
B3
B4
HI-Z
HI-Z
LSB first data begins
to come out
LSB first data begins
to come out
© 2007 Microchip Technology Inc.
MCU latches data from ADC
on rising edges of SCLK
MCU latches data from ADC
on rising edges of SCLK
Data is clocked out of
ADC on falling edges
Data is clocked out of
ADC on falling edges