AD9876ABST Analog Devices Inc, AD9876ABST Datasheet - Page 17

• Manufacturer Part Number: AD9876ABST
• Description: IC 12BIT MODEM MXFE 48-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9876ABST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 1
• Power (watts): 950mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 48-LQFP
• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

The digital data outputs of the ADC are represented in two’s
complement format. They saturate to full scale or zero when the
input signal exceeds the input voltage range.
The twos complement data format is shown below:
The maximum value will be output from the ADC when the
Rx+ input is 1 V or more greater than the Rx– input. The mini-
mum value will be output from the ADC when the Rx– input is
1 V or more greater than the Rx+ input. This results in a full-
scale ADC voltage of 2 Vppd.
The data can be translated to straight binary data format by
simply inverting the most significant bit.
The best ADC performance will be achieved when the ADC
clock source is selected from f
from a low jitter clock source. The amount of degradation from
jitter on the ADC clock will depend on how quickly the input is
varying at the sampling instance. TPC 36 charts this effect in
the form of ENOB vs. input frequency for the two clocking
scenarios.
The maximum sample rate of the ADC in Full-Precision Mode,
that is outputting 12 bits, is 55 MSPS. TPC 33 shows the ADC
performance in ENOB versus f
of the ADC in Half-Precision Mode, that is outputting five bits,
is 64 MSPS. The timing of the interface is fully described in the
Receive Port Timing section of this data sheet.
DIGITAL HPF
Following the ADC, there is a bypassable digital HPF. The
response is a single-pole IIR HPF. The transfer function is:
where the sampling period is equal to the ADC clock period.
This results in a 3 dB frequency approximately 1/400th of the
ADC sampling rate. The transfer functions are plotted for
32 MSPS and 50 MSPS in TPC 29 and TPC 32.
The digital HPF introduces a 1 ADC clock cycle latency. If the
HPF function is not desired, the HPF can be bypassed and the
latency will not be incurred.
REV. A
011 . . 11: Maximum
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB
111 . . 10: Midscale – 2 LSB
100 . . 00: Minimum
AINP
AINN
H z
Figure 2. ADC Theory of Operation
A/D
( )
SHA
=
D/A
(
1 0 99994
– .
GAIN
OSCIN
CORRECTION LOGIC
ADC
Z
–
. The maximum sample rate
and the OSCIN pin is driven
1
) (
A/D
1 98466
SHA
–
D/A
AD9876
GAIN
Z
–
1
)
A/D
–17–
CLOCK AND OSCILLATOR CIRCUITRY
The AD9876’s internal oscillator generates all sampling clocks
from a fundamental frequency quartz crystal. Figure 3a shows
how the quartz crystal is connected between OSCIN (Pin 1) and
XTAL (Pin 48) with parallel resonant load capacitors as speci-
fied by the crystal manufacturer. The internal oscillator circuitry
can also be overdriven by a TTL-level clock applied to OSCIN
with XTAL left unconnected.
The PLL has a frequency capture range between 10 MHz
and 64 MHz.
VOLTAGE REGULATOR CONTROLLER
The AD9876 contains an on-chip voltage regulator controller
(VRC) for providing a linear 1.3 V supply for low voltage digital
circuitry or other external use. The VRC consists of an op amp
and a resistive voltage divider. As shown in Figure 3b, the resis-
tive divider establishes a voltage of 1.3 V at the inverting input
of the amplifier when DVDD is equal to its nominal voltage of
3.3 V. The feedback loop around the op amp will adjust the gate
voltage such that the voltage at the FB pin, V
the voltage at the inverting input of the op amp.
The maximum current output from the circuit is largely depen-
dent on the MOSFET device. For the SI2301 shown, 250 mA
can be delivered. The regulated output voltage should have bulk
decoupling and high frequency decoupling capacitors to ground
as required by the load. The regulator circuit will be stable for
capacitive loads between 0.1 µF and 47 µF.
It should be noted that the regulated output voltage, V
proportional to DVDD. Therefore, the percentage variation in
DVDD will also be seen at the regulated output voltage. The
load regulation is roughly equal to the ON resistance of the
MOSFET device chosen. For the SI2301, this is about 60 mΩ.
Figure 3a. Connections for a Fundamental Mode Crystal
Figure 3b. Connections for 1.3 V Linear Regulator
1.3R
2R
DVDD
AD9876
AD9876
3.3V
OSCIN
XTAL
GATE
FB
V
C1
FB
XTAL
= 1.3V
G
Y1
S
D
C2
FB
SI2301
, will be equal to
C
AD9876
V
OUT
FB
, is