AD73322LYRU Analog Devices Inc, AD73322LYRU Datasheet - Page 35

• Manufacturer Part Number: AD73322LYRU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LYRU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT
In some applications it may be desirable to convert the full
differential output of the decoder channel to a single-ended
signal. The circuit of Figure 42 shows a scheme for doing this.
R
DIGITAL INTERFACING
The AD73322L is designed to interface easily to most common
DSPs. The SCLK, SDO, SDOFS, SDI, and SDIFS must be con-
nected to the DSP’s serial clock, receive data, receive data
frame sync, transmit data, and transmit data frame sync pins,
respectively. The SE pin may be controlled from a parallel
output pin or flag pin such as FL0-2 on the ADSP-21xx (or XF
on the TMS320C5x) or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. The RESET pin may be connected to the
system hardware reset structure or it may also be controlled
using a dedicated control line. In the event of tying it to the
global system reset, it is advisable to operate the device in mixed
mode, which allows a software reset, otherwise there is no
convenient way of resetting the device. Figure 43 and Figure 44
show typical connections to an ADSP-218x and TMS320C5x,
respectively.
LOAD
Figure 42. Example Circuit for Differential to Single-Ended
R
ADSP-218x
F
R
F
DSP
Figure 43. AD73322L Connected to ADSP-218x
R1
R1
VOUTP1
VOUTN1
REFOUT
REFCAP
0.1µF
VFBP1
VINP1
TFS
DT
SCLK
DR
RFS
FL0
FL1
Output Conversion
V
REF
+6/–15dB
SDOFS
RESET
PGA
SDIFS
SCLK
REFERENCE
SDO
SDI
SE
GAIN
CONTINUOUS
±1
LOW-PASS
FILTER
AD73322L
TIME
CODEC
AD73322L
V
REF
0/38dB
PGA
Rev. A | Page 35 of 48
CASCADE OPERATION
Where it is required to configure a cascade of up to eight codecs
(four AD73322L dual codecs), ensure that the timing of the SE
and RESET signals is synchronized at each device in the
cascade. A simple D-type flip-flop is sufficient to sync each
signal to the master clock MCLK, as in Figure 45.
Connection of a cascade of devices to a DSP, as shown in
Figure 46, is no more complicated than connecting a single
device. Instead of connecting the SDO and SDOFS to the DSP’s
Rx port, these are now daisy-chained to the SDI and SDIFS of
the next device in the cascade. The SDO and SDOFS of the final
device in the cascade are connected to the DSP’s Rx port to
complete the cascade. SE and RESET on all devices are fed from
the signals that were synchronized with the MCLK using the
circuit, as described previously. The SCLK from only one device
need be connected to the DSP’s SCLK input(s) as all devices run
at the same SCLK frequency and phase.
Figure 45. SE and RESET Sync Circuit or Cascaded Operation
DSP CONTROL
DSP CONTROL
TMS320C5x
TO RESET
DSP
Figure 44. AD73322L Connected to TMS320C5x
TO SE
MCLK
MCLK
D
CLK
D
CLK
FSX
DT
CLKX
CLKR
DR
FSR
XF
74HC74
74HC74
1/2
1/2
Q
Q
SE SIGNAL SYNCHRONIZED
TO MCLK
RESET SIGNAL SYNCHRONIZED
TO MCLK
SDOFS
RESET
SDIFS
SCLK
SDO
SDI
SE
AD73322L
CODEC
AD73322L