AD73322AST Analog Devices Inc, AD73322AST Datasheet - Page 26

• Manufacturer Part Number: AD73322AST
• Description: IC ANALOG FRONT END DUAL 44-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD73322AST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 44-LQFP

AD73322
INTERFACING
The AD73322 can be interfaced to most modern DSP engines
using conventional serial port connections and an extra enable
control line. Both serial input and output data use an accompa-
nying frame synchronization signal that is active high one clock
cycle before the start of the 16-bit word or during the last bit of
the previous word if transmission is continuous. The serial clock
(SCLK) is an output from the codec and is used to define the
serial transfer rate to the DSP’s Tx and Rx ports. Two primary
configurations can be used: the first is shown in Figure 18 where
the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync
are connected to the codec’s SDI, SDIFS, SDO and SDOFS
respectively. This configuration, referred to as indirectly coupled or
nonframe sync loop-back, has the effect of decoupling the trans-
mission of input data from the receipt of output data. The delay
between receipt of codec output data and transmission of input
data for the codec is determined by the DSP’s software latency.
When programming the DSP serial port for this configuration, it
is necessary to set the Rx FS as an input and the Tx FS as an
output generated by the DSP. This configuration is most useful
when operating in mixed mode, as the DSP has the ability to
decide how many words (either DAC or control) can be sent to
the codecs. This means that full control can be implemented
over the device configuration as well as updating the DAC in a
given sample interval. The second configuration (shown in
Figure 19) has the DSP’s Tx data and Rx data connected to the
codec’s SDI and SDO, respectively, while the DSP’s Tx and Rx
frame syncs are connected to the codec’s SDIFS and SDOFS.
In this configuration, referred to as directly coupled or frame
sync loop-back, the frame sync signals are connected together
and the input data to the codec is forced to be synchronous with
the output data from the codec. The DSP must be programmed
so that both the Tx FS and Rx FS are inputs as the codec
SDOFS will be input to both. This configuration guarantees
that input and output events occur simultaneously and is the
simplest configuration for operation in normal Data Mode.
Note that when programming the DSP in this configuration it is
advisable to preload the Tx register with the first control word
to be sent before the codec is taken out of reset. This ensures
that this word will be transmitted to coincide with the first out-
put word from the device(s).
Figure 18. Indirectly Coupled or Nonframe Sync Loop-
Back Configuration
ADSP-21xx
DSP
TFS
DT
SCLK
DR
RFS
SDOFS
SDIFS
SCLK
SDO
SDI
CODEC1
CODEC2
AD73322
CODEC
–26–
Cascade Operation
The AD73322 has been designed to support cascading of
codecs from a single DSP serial port (see Figure 31). Cascaded
operation can support mixes of dual or single channel devices
with the maximum number of codec units being eight (the
AD73322 is equivalent to two codec units). The SPORT inter-
face protocol has been designed so that device addressing is
built into the packet of information sent to the device. This
allows the cascade to be formed with no extra hardware over-
head for control signals or addressing. A cascade can be formed
in either of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the sampling
rate and serial clock rate chosen. The following relationship
details the restrictions in configuring a codec cascade.
When using the indirectly coupled frame sync configuration in
cascaded operation, it is necessary to be aware of the restrictions
in sending data to all devices in the cascade. Effectively the time
allowed is given by the sampling interval (M/DMCLK—where
M can be one of 256, 512, 1024 or 2048), which is 125 s for a
sample rate of 8 kHz. In this interval, the DSP must transfer
N 16 bits of information where N is the number of devices in
the cascade. Each bit will take 1/SCLK and, allowing for any
latency between the receipt of the Rx interrupt and the trans-
mission of the Tx data, the relationship for successful operation
is given by:
The interrupt latency will include the time between the ADC
sampling event and the Rx interrupt being generated in the
DSP—this should be 16 SCLK cycles.
As the AD73322 is configured in cascade mode, each device
must know the number of devices in the cascade because the
data and mixed modes use a method of counting input frame
sync pulses to decide when they should update the DAC register
from the serial input register. Control Register A contains a 3-bit
field (DC0-2) that is programmed by the DSP during the pro-
gramming phase. The default condition is that the field contains
000b, which is equivalent to a single device in cascade (see
Table XXII). However, for cascade operation this field must
contain a binary value that is one less than the number of de-
vices in the cascade, which is 001b for a single AD73322 device
configuration.
Number of Codecs
ADSP-21xx
Figure 19. Directly Coupled or Frame Sync Loop-
Back Configuration
M/DMCLK > ((N
DSP
TFS
DT
SCLK
DR
RFS
Word Size (16) Sampling Rate <= Serial
16/SCLK) + T
Clock Rate
SDOFS
SDIFS
SCLK
SDO
SDI
INTERRUPT LATENCY
CODEC1
CODEC2
AD73322
CODEC
REV. B
)