MAX5865ETM+T Maxim Integrated Products, MAX5865ETM+T Datasheet
MAX5865ETM+T
Specifications of MAX5865ETM+T
Related parts for MAX5865ETM+T
MAX5865ETM+T Summary of contents
Page 1
... Exposed paddle. **Contact factory for dice specifications. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Ultra-Low-Power, High-Dynamic- o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs o Ultra-Low Power 75 ...
Page 2
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND OGND................................-0.3V to +3. GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V ...
Page 3
Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
Page 4
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...
Page 5
Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
Page 6
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...
Page 7
Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
Page 8
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
Page 9
Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
Page 10
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
Page 11
Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
Page 12
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End PIN NAME 1 REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass 0.1µF capacitor. 3 ...
Page 13
Performance, 40Msps Analog Front End Detailed Description The MAX5865 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conver- sion rate of 40Msps. The ADCs’ analog input amplifiers are ...
Page 14
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed con- version while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. ...
Page 15
Performance, 40Msps Analog Front End ADC System Timing Requirements Figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. Channel IA (CHI) and channel QA (CHQ) are simultaneously sam- pled on the rising edge ...
Page 16
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode V 1.024V, External Reference Mode V DIFFERENTIAL OUTPUT VOLTAGE V 1023 REFDAC × 2.56 1023 V 1021 REFDAC × 2.56 1023 V ...
Page 17
Performance, 40Msps Analog Front End Table 3. MAX5865 Operation Modes FUNCTION DESCRIPTION D evi ce shutd off off, and the ...
Page 18
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End CSS CP SCLK t DS DIN MSB t DH Figure 5. 3-Wire Serial Interface Timing Diagram CS SCLK DIN 8-BIT DATA DAO–DA7 ID/QD Figure 6. MAX5865 Mode Recovery Timing Diagram ...
Page 19
Performance, 40Msps Analog Front End Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX5865 clock input operates with an ...
Page 20
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ID+ MAX5865 ID- QD+ QD- Figure 8. Balun-Transformer Coupled Differential to Single- Ended Output Drive for DACs REFP 1kΩ ISO IN 0.1µF 50Ω 22pF 100Ω 1kΩ REFN 0.1µF R ...
Page 21
Performance, 40Msps Analog Front End R1 600Ω R2 600Ω R3 600Ω Figure 10. ADC DC-Coupled Differential Drive T/R Figure 11. Typical Application Circuit for TDD ______________________________________________________________________________________________________ Ultra-Low-Power, High-Dynamic 600Ω 600Ω R ISO 22Ω 600Ω 600Ω R8 ...
Page 22
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End range, it can interface directly with RF transceivers while eliminating discrete components and amplifiers used for level-shifting circuits. Also, the DAC’s full dynamic range is preserved because the internally generated common- mode level ...
Page 23
Performance, 40Msps Analog Front End Offset error (Figure 12a) is the difference between the ideal and actual offset point. The offset point is the out- put value when the digital input is midscale. This error affects all codes by the ...
Page 24
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ...
Page 25
Performance, 40Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) D D/2 ______________________________________________________________________________________ Ultra-Low-Power, High-Dynamic- k E/2 (NE- DETAIL ...
Page 26
... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Package Information (continued) ** NOTE: T4877 CUSTOM 48L PKG ...