AD73311ARZ Analog Devices Inc, AD73311ARZ Datasheet - Page 34

• Manufacturer Part Number: AD73311ARZ
• Description: IC PROCESSOR FRONT END LP 20SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73311ARZ

• Number Of Bits: 16
• Number Of Channels: 2
• Power (watts): 50mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 20-SOIC (7.5mm Width)
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 1
• No. Of Output Channels: 1
• Adc / Dac Resolution: 16bit
• Adcs / Dacs Signal To Noise Ratio: 75dB
• Sampling Rate: 64kSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD73311
APPENDIX E
DAC Timing Control Example
The AD73311’s DAC is loaded from the DAC register contents
just before the ADC register contents are loaded to the serial
register (SDOFS going high). This default DAC load position
can be advanced in time to occur earlier with respect to the
SDOFS going high. Figure 37 shows an example of the ADC
unload and DAC load sequence. At time t
to indicate that a new ADC word is ready. Following the SDOFS
pulse, 16 bits of ADC data are clocked out on SDO in the sub-
sequent 16 SCLK cycles finishing at time t
SPORT will have received the 16-bit word. The DSP may
FROM DAC REGISTER
DAC REGISTER
DAC LOAD
UPDATE
SDOFS
SDIFS
SCLK
SDO
SDI
SE
t
1
1
2
the SDOFS is raised
where the DSP’s
ADC WORD
t
2
process this information and generate a DAC word to be sent to
the AD73311. Time t
sending the DAC word to the AD73311. This sequence ends at
time t
in the AD73311’s serial register. However, the DAC will not be
updated from the DAC register until time t
acceptable in certain applications. In order to reduce this delay
and load the DAC at time t
programmed with a suitable setting corresponding to the
required time advance (refer to Table VIII for details of DAC
Timing Control settings).
t
3
4
where the DAC register will be updated from the 16 bits
DAC WORD
t
4
t
6
3
marks the beginning of the sequence of
6
, the DAC advance register can be
t
5
5
which may not be