MCP3901A0-I/SS Microchip Technology, MCP3901A0-I/SS Datasheet
MCP3901A0-I/SS
Specifications of MCP3901A0-I/SS
MCP3901AO-I/SS
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MCP3901A0-I/SS Summary of contents
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... Energy Metering & Power Measurement • Automotive • Portable Instrumentation • Medical and Power Monitoring © 2009 Microchip Technology Inc. Description The MCP3901 is a dual channel analog front end (AFE) containing two synchronous sampling delta-sigma Analog-to-Digital Converters (ADC), two PGAs, phase ...
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... PHASE <7:0> F Shifter DATA_CH1<23:0> SINC Modulator SDN<1:0>, RESET<1:0>, GAIN<7:0> MOD<7:0> POR AGND DGND Xtal Oscillator OSC1 MCLK Clock Generation OSC2 OSR<1:0> DMCLK PRE<1:0> DR SDO Digital SPI RESET Interface SDI SCK CS MODOUT<1:0> Modulator MDAT0 Output Block MDAT1 © 2009 Microchip Technology Inc. ...
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... BOOST bits off. With BOOST bits on, AMCLK should be in the range 8.192 MHz. AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to 0. © 2009 Microchip Technology Inc. † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device ...
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... From -40°C to +125°C ppm GAIN = 1, DITHER = ON kΩ Proportional to 1/AMCLK dB OSR = 256, DITHER = OSR = 256, DITHER = OSR = 256, DITHER = OSR = 256, DITHER = ON dB OSR = 256, DITHER = 2.4V. REF Figure 2-19 for typical values. © 2009 Microchip Technology Inc. ...
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... Electrical Specifications: Unless otherwise indicated, all parameters apply 2.7 to 5.5V, -40°C < T <+85° Parameters Serial Clock frequency CS setup time Note 1: This parameter is periodically sampled and not 100% tested. © 2009 Microchip Technology Inc. = 4.5 to 5.5V -0.5 dBFS = 353 mV IN Min Typical Max — -77 — ...
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... V SDO pin only +2 and MDAT pins only +800 mA, V =5. SDO pin only -2 and MDAT pins only -800 µA, V =5. µ DGND µ DGND DD OUT 25°C, A SCK = 1.0 MHz 5.0V (Note 1) DD © 2009 Microchip Technology Inc. ...
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... Serial Output Timing Diagram CSS Mode 1,1 Mode 0,0 SCK SDI MSB in SDO FIGURE 1-2: Serial Input Timing Diagram. © 2009 Microchip Technology Inc. Min Typ Max -40 — +85 A -65 — +150 A — 89.3 — must not exceed the absolute maximum specification of +150°C. ...
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... MCP3901 Clock Detail. DS22192B-page DRCLK Timing Waveform for SDO t DOMDAT PRESCALE<1:0> Prescale AMCLK MCLK Clock Divider Clock Divider t DRP DIS V IH 90% t HI-Z DIS 10% OSR<1:0> f ADC f ADC D S Output Sampling Data Rate Rate 1 / OSR DMCLK DRCLK Clock Divider © 2009 Microchip Technology Inc. ...
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... OSR = 256 -60 16384 points Dithering OFF -80 -100 -120 -140 -160 -180 -200 0 500 1000 1500 Frequency (Hz) FIGURE 2-3: Spectral Response. © 2009 Microchip Technology Inc. = 5.0V 5 +25°C, MCLK = 4 MHz; PRESCALE = -0.5dBFS @ 60 Hz -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 ...
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... OSR = 256 Dithering FIGURE 2-12: Distortion vs. Gain. Dithering ON Dithering OFF 32 64 128 256 Oversampling Ratio (OSR) Spurious Free Dynamic Dithering 128 256 Oversampling Ratio (OSR) Signal-to-Noise and OSR = 256 OSR = 128 OSR = 32 OSR = Gain (V/V) Signal-to-Noise and © 2009 Microchip Technology Inc. ...
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... Oversampling Ratio. 100 15.625 ksps -20 -40 -60 SINC filter notch at 15.625 Hz -80 10 100 1000 Input Signal Frequency (Hz) FIGURE 2-15: Total Harmonic Distortion vs. Input Signal Frequency. © 2009 Microchip Technology Inc. = 5.0V 5 +25°C, MCLK = 4 MHz; PRESCALE = -0.5dBFS @ 60 Hz MCLK = 4 MHz 12 OSR = 256 Dithering ...
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... Match vs. Temperature. G=8 G=16 G=1 G=32 G=2 G 100 125 150 Temperature (ºC) Channel 0 Offset vs. G=8 G=1 G=16 G=32 G=2 G=4 - 100 125 150 Temperature (°C) Channel 1 Offset vs. Channel 0 Channel 1 - 100 125 150 Temperature (°C) Channel-to-Channel Offset © 2009 Microchip Technology Inc. ...
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... Negative Gain Error vs. Temperature 2.4 2.39 2.38 2.37 2.36 2.35 -50 - Temperature (°C) FIGURE 2-27: Internal Voltage Reference vs. Temperature. © 2009 Microchip Technology Inc. = 5.0V 5 +25°C, MCLK = 4 MHz; PRESCALE = -0.5dBFS @ 60 Hz. IN 2.37165 2.3716 G=1 G=2 2.37155 G=8 2.3715 G=16 2.37145 G=4 2 ...
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... Input Voltage (V) FIGURE 2-32: Integral Non-Linearity (Dithering On). DS22192B-page 14 = 5.0V 5 25°C, MCLK = 4 MHz; PRESCALE = -0.5dBFS @ 60 Hz. IN 2.5 2 1.5 1 0 FIGURE 2-33: Master Clock (MCLK). 0.5 AI BOOST OFF MCLK (MHz) Operating Current vs. © 2009 Microchip Technology Inc. ...
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... All the analog biases are enabled during a reset so that the part is fully operational just after a RESET rising edge. This input is Schmitt triggered. © 2009 Microchip Technology Inc. Table 3-1. Function 3.2 Digital V ...
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... The DR pulse width is equal to one DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3). Note: This pin should not be left floating when DR_HIZN bit is low kΩ pull-up resistor connected the MCLK frequency, is recommended. VDD © 2009 Microchip Technology Inc. ...
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... The maximum clock speed specified is 20 MHz when DV >4.5V and 10 MHz otherwise. DD This input is Schmitt triggered. © 2009 Microchip Technology Inc. 3.14 SDO (Serial Data Output) This is the SPI data output pin. Data is clocked out of the device on the FALLING edge of SCK. ...
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... MCP3901 NOTES: DS22192B-page 18 © 2009 Microchip Technology Inc. ...
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... OSC1/OSC2 inputs when CLKEXT=0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT=1. See Figure 1-5. © 2009 Microchip Technology Inc. MCP3901 4.2 AMCLK - Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG1 PRESCALE< ...
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... REF ).This REF Figure 2-24 and Figure 2-25. © 2009 Microchip Technology Inc. ...
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... SINAD log 10 + © 2009 Microchip Technology Inc. 4.11 Total Harmonic Distortion (THD) The total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation. EQUATION 4-7: ( THD dB The THD calculation includes the first 35 harmonics for the MCP3901 specifications ...
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... SINAD, THD, SFDR) are less signal dependent. The MCP3901 incorporates a proprietary dithering algorithm on both ADCs in order to remove idle tones and improve THD, which is crucial for power metering applications. Figure 2-10 and © 2009 Microchip Technology Inc. ...
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... DC values (the power supply is a sinewave at a certain frequency with a certain common mode). In AC, the amplitude of the sinewave is representing the change in the power supply defined as: © 2009 Microchip Technology Inc. EQUATION 4-11: PSRR dB Where V is the equivalent input voltage that the ...
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... MCLK edge coming while on this mode will induce and dynamic power consumption. POR Once any of the SHUTDOWN, CLKEXT and VREFEXT bits returns to 0, the POR AV back to operation and AV mode will resynchronize VDD monitoring block is DD monitoring can take place. DD © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. 5.3 Delta-Sigma Modulator 5.3.1 ARCHITECTURE Both ADCs are identical in the MCP3901 and they include a second-order modulator with a multi-bit DAC architecture (see ADC composed of 4 comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum ...
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... This means that the first output of MDAT after RESET is always 0011 after the first DMCLK rising edge. DELTA-SIGMA MODULATOR CODING Modulator MDAT Serial Output Code Stream +2 1111 +1 0111 0 0011 -1 0001 -2 0000 COMP COMP COMP <0> <1> <2> MDAT Serial Outputs in © 2009 Microchip Technology Inc. ...
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... OSR 1 z – Where: ⎛ ⎞ 2πfj --------------------- - z = exp ⎝ ⎠ DMCLK © 2009 Microchip Technology Inc. The Normal-Mode Rejection Ratio (NMRR) or gain of the transfer function is given by the following equation: EQUATION 5-2: NMRR or: ADC NMRR Resolution (bits) No Missing Codes where ...
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... Equation 5-1 5-2). (For 24-bit Mode Or WIDTH = 1) (For 16-bit Mode Or WIDTH = 0) Hexadecimal Decimal 0x7FFFFF + 8,388,607 0x7FFFFE + 8,388,606 0x000000 0 0xFFFFFF -1 0x800001 - 8,388,607 0x800000 - 8,388,608 Decimal Hexadecimal 23-bit Resolution 0x7FFFFE + 4,194,303 0x7FFFFC + 4,194,302 0x000000 0 0xFFFFFE -1 0x800002 - 4,194,303 0x800000 - 4,194,304 © 2009 Microchip Technology Inc. ...
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... REFIN+/OUT and AGND. De-coupling at the sampling frequency, around 1 MHz, is important for any noise around this frequency will be aliased back into the conversion data. 0.1 µF ceramic and 10 µF tantalum capacitors are recommended. © 2009 Microchip Technology Inc. Hexadecimal ...
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... Note: A detailed explanation of the data ready pin (DR) with phase delay is present in Section 6.10 “Data Ready Latches And Data Ready Modes (DRMODE<1:0>)”. Phase Register Code = ------------------------------------------------- - DMCLK © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. 5.11 Crystal Oscillator The MCP3901 includes a Pierce type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies provided that proper load capacitances and quartz quality factor are used ...
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... MCP3901 NOTES: DS22192B-page 32 © 2009 Microchip Technology Inc. ...
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... A<6:5>) so that multiple MCP3901 chips can be present on the same SPI bus with no data bus contention. This functionality enables three-phase power metering systems containing three MCP3901 chips controlled by a single SPI bus (single CS, SCK, SDI and SDO pins). © 2009 Microchip Technology Inc Device Address Bits FIGURE 6-1: The default device address bits are 00 ...
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... Bits on the Rising Edge SCK SDI HI-Z HI-Z SDO FIGURE 6-4: Device Read (SPI Mode 0,0 - Clock Idles Low). DS22192B-page 34 R (ADDRESS) DATA (ADDRESS + 1) DATA A0 R (ADDRESS) DATA (ADDRESS + 1) DATA HI-Z R (ADDRESS) DATA (ADDRESS + 1) DATA HI HI-Z HI (ADDRESS + 2) DATA D0 © 2009 Microchip Technology Inc. ...
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... CH0 ADC CH0 ADC SDO Upper byte Middle byte Lower byte DR These bytes are not present when WIDTH=0 (16-bit mode) FIGURE 6-6: Typical Continuous Read Communication. © 2009 Microchip Technology Inc R (ADDRESS) DATA (ADDRESS + 1) DATA HI-Z The STATUS/COM register contains the loop settings for the internal address counter (READ< ...
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... PHASE ADDR/W PHASE GAIN STATUS/COM One command for writing complete configuration REGISTER GROUPS ADDRESSES 0x00 - 0x02 0x03 - 0x05 0x06 - 0x08 0x09 - 0x0B REGISTER TYPES ADDRESSES 0x00 - 0x05 0x06 - 0x0B xxxxxxxx xxxxxxxx xxxxxxxx CONFIG1 CONFIG2 © 2009 Microchip Technology Inc. ...
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... The DR pin can be used as an interrupt when connected to a MCU or DSP. While RESET pin is low, the DR pin is not active. © 2009 Microchip Technology Inc. 6.10 Data Ready Latches And Data Ready Modes (DRMODE<1:0>) To ensure that both channel ADC data are present at ...
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... DR pulse for the ADC not in shutdown or reset, i.e. only 1 ADC channel needs to be awake. DS22192B-page 38 Figure 6-8 represents the behavior of the data ready pin with the different DRMODE and DR_LTY configurations, while shutdown or resets are applied. © 2009 Microchip Technology Inc. ...
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... PHASE < 0 FIGURE 6-8: Data Ready Behavior. © 2009 Microchip Technology Inc. PHASE = 0 PHASE > 0 MCP3901 DS22192B-page 39 ...
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... MCP3901 NOTES: DS22192B-page 40 © 2009 Microchip Technology Inc. ...
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... PHASE 0x07 GAIN 0x08 STATUS/ 0x09 COM CONFIG1 0x0A CONFIG2 0x0B © 2009 Microchip Technology Inc. read R Channel 0 ADC Data <23:0>, MSB First 24 R Channel 1 ADC Data <23:0>, MSB First 8 R/W Delta Sigma Modulators Output Register 8 R/W Phase Delay Configuration Register ...
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... DATA_CHn <4> <3> <2> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 DATA_CHn DATA_CHn <17> <16> bit 16 R-0 R-0 DATA_CHn DATA_CHn <9> <8> bit 8 R-0 R-0 DATA_CHn DATA_CHn <1> <0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: This register can be written in order to overwrite modulator output data but any writing here will corrupt the ADC_DATA on the next three data ready pulses. © 2009 Microchip Technology Inc. This register should be used as a read-only register. (Note 1). This register is updated at the refresh rate of DMCLK (typically 1 MHz with MCLK=4 MHz). See Section 5.4 “ ...
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... OSR=32: the delay can go from -16 to +15. PHASE<4> is the sign bit. Phase<3> is the MSB and PHASE<0> the LSB R/W-0 R/W-0 R/W-0 PHASE<4> PHASE<3> PHASE<2> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PHASE<1> PHASE<0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PGA_CH0<2:0>: PGA Setting for Channel 0 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 BOOST_ BOOST_ PGA_CH0 CH1 CH0 < ...
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... In case the DRMODE=00 (Linked ADCs), these data ready status bits will be updated synchronously upon the same event (lagging ADC is ready). These bits are also useful in systems where the DR pin is not used to save MCU I/O. © 2009 Microchip Technology Inc. output pin ...
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... ADC Channel 1 and Channel 0 data not ready (Default ADC Channel 1 data not ready, ADC Channel 0 data ready 01 = ADC Channel 0 data not ready, ADC Channel 1 data ready 00 = ADC Channel 1 and Channel 0 data ready © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DR_HIZN DRMODE< ...
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... WIDTH WIDTH _CH1 _CH0 R/W-0 R/W-1 R/W-1 SHUTDOWN DITHER DITHER _CH0 _CH1 _CH0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MODOUT MODOUT _CH1 _CH0 bit 8 R/W-0 R/W-0 VREFEXT CLKEXT bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Internal Voltage Reference Disabled, an external voltage reference must be placed between REFIN+/OUT and REFIN Internal Voltage Reference Enabled (default) bit 0 CLKEXT Clock Mode 1 = External clock mode (Internal Oscillator Disabled and bypassed - Lower Power Mode - A crystal must be placed between OSC1/OSC2 (default) © 2009 Microchip Technology Inc. MCP3901 DS22192B-page 49 ...
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... MCP3901 NOTES: DS22192B-page 50 © 2009 Microchip Technology Inc. ...
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... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. MCP3901 Example: MCP3901A0 e I/SS^^ 3 922256 ...
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... MCP3901 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± 1RWH 1RWHV DS22192B-page 52 PP %RG\ >6623@ I © 2009 Microchip Technology Inc. φ ...
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... APPENDIX A: REVISION HISTORY Revision B (November 2009) The following is the list of modifications: 1. Removed the QFN package and all references to it. Revision A (September 2009) • Original Release of this Document. © 2009 Microchip Technology Inc. MCP3901 DS22192B-page 53 ...
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... MCP3901 NOTES: DS22192B-page 54 © 2009 Microchip Technology Inc. ...
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... Examples: a) Package Range MCP3901 . Two Channel ΔΣ A/D MCP3901A0-I/SS: Converter, SSOP-20 package, Address Option = A0 MCP3901A0T-I/SS: Tape and Reel, Two Channel ΔΣ A/D Converter, SSOP-20 package, Address Option = A0 Two Channel ΔΣ A/D MCP3901A1-I/SS: Converter, SSOP-20 package, Address Option = A1 MCP3901A1T-I/SS: Tape and Reel, Two Channel Δ ...
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... MCP3901 NOTES: DS22192B-page 56 © 2009 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...