DS14285Q+ Maxim Integrated Products, DS14285Q+ Datasheet
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DS14285Q+
Specifications of DS14285Q+
Related parts for DS14285Q+
DS14285Q+ Summary of contents
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FEATURES Direct Replacement for IBM AT Computer Clock/Calendar Functionally Compatible with the DS1285/DS1287 Available as Chip (DS14285, DS14285S, or DS14285Q) or Stand-Alone Module with Embedded Lithium Battery and Crystal (DS14287) Automatic Backup Supply and Write Protection to Make External ...
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... DS14285 0°C to +70°C DS14285+ 0°C to +70°C DS14285N -40°C to +85°C DS14285N+ -40°C to +85°C DS14285Q 0°C to +70°C DS14285Q+ 0°C to +70°C DS14285QN -40°C to +85°C DS14285QN+ -40°C to +85°C DS14285S 0°C to +70°C DS14285S+ 0°C to +70°C DS14285SN -40° ...
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DETAILED DESCRIPTION The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287 clock function with the additional feature of providing nonvolatile control for an external SRAM. Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt, ...
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MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When connected Motorola bus timing is selected. When connected to GND or left disconnected, Intel CC bus timing is selected. The ...
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Input) - The RESET RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time RESET that is held low is dependent on the application. However, if RESET ...
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The battery should be connected directly to the V battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories ...
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POWER-DOWN/POWER-UP CONSIDERATIONS The real time clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the V DS14285/DS14287 and reaches a level of greater than 4.25 ...
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RTC ADDRESS MAP The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes ...
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When the 12-hour format is selected, the high order bit of the hours byte represents PM when logic one. The time, calendar, and alarm bytes are always ...
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CONTROL REGISTERS The DS14285/DS14287 has four control registers that are accessible at all times, even during the update cycle. REGISTER A MSB BIT 7 BIT 6 UIP DV2 UIP - The Update In Progress (UIP) bit is a status flag ...
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REGISTER B MSB BIT 7 BIT 6 SET PIE SET - When the SET bit the update transfer functions normally by advancing the counts once per second. When the SET bit is written any ...
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REGISTER C MSB BIT 7 BIT 6 IRQF PF IRQF - The Interrupt Request Flag (IRQF) bit is set when one or more of the following are true PIE = AIE = ...
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NONVOLATILE RAM The 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within the DS14285/DS14287. They can be used by the processor program as nonvolatile memory and are fully available during the update cycle. The DS14285/DS14287 can ...
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Register C is read. Double latching is included with Register C so that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared when ...
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Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency SELECT BITS REGISTER A RS3 RS2 RS1 ...
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Figure 4. Update-Ended and Periodic Interrupt Relationship ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +7.0V Storage Temperature Range………………………………………………………………...-40°C to +85°C Soldering Temperature: DIP…………………………………………..260°C for 10 seconds (See Note 12) Soldering Temperature: Surface Mount:…………………………….See IPC/JEDEC Standard J-STD-020 This is a stress rating only ...
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AC ELECTRICAL CHARACTERISTICS (Over the operating range) PARAMETER Cycle Pulse Width, DS/E Low or RD/ High Pulse Width, DS/E Low or RD/ Low Input Rise and Fall Time R/ Hold Time W R/ Setup Time Before DS/E W Chip Select ...
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Figure 5. Output Load DS14285 BUS TIMING FOR MOTOROLA INTERFACE ...
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DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE WRITE CYCLE ...
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DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE READ CYCLE DS14285/DS14287 IRQ RELEASE DELAY TIMING ...
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POWER-DOWN/POWER-UP TIMING POWER-DOWN/POWER-UP TIMING PARAMETER at V before Power-Down slew from 4. slew from after Power- Chip-Enable Propagation Delay to External ...
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NOTES: 1) All voltages are referenced to ground. 2) All outputs are open. 3) The MOT pin has an internal pulldown of 20kΩ. 4) The pin has an internal pullup of 50kΩ. CEI 5) Applies to the AD0–AD7 pins, the ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14285 24-PIN DIP DS14285 24-PIN SO PKG 24-PIN DIM MIN MAX A IN. 1.245 1.270 ...
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PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14285Q 28-PIN PLCC PKG DIM ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. NOTE: PINS 2, 3, 16, AND 20 ARE MISSING BY DESIGN. ...