ISL12029IB27AZ Intersil, ISL12029IB27AZ Datasheet - Page 14

• Manufacturer Part Number: ISL12029IB27AZ
• Description: IC RTC/CALENDAR EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IB27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
controlled capacitors, C
and X2 pins to ground (see Figure 11). The value of C
C
The effective series load capacitance is the combination of
C
For example, CLOAD(ATR = 00000) = 12.5pF,
C
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note
that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
C
C
C X
X2
X1
LOAD
LOAD
LOAD
DTR2
=
is given by Equation 1:
and C
0
(
16 b5
(ATR = 100000) = 4.5pF, and C
=
=
DTR REGISTER
⋅
⎛
⎝
TABLE 5. DIGITAL TRIMMING REGISTERS
---------------------------------- -
⎛
⎝
X2
---------- -
C
16 b5
---------------------------------------------------------------------------------------------------------------------------- -
1
X1
+
⋅
DTR1
given in Equation 2:
X1
X2
8 b4
1
+
FIGURE 12. DIAGRAM OF ATR
0
⋅
---------- -
C
+
1
8 b4
X2
LOAD
+
⋅
C
C
4 b3
⎞
⎠
X1
X2
⋅
+
X1
DTR0
4 b3
is changed via two digitally
+
⋅
0
and C
2 b2
⋅
14
+
2 b2
2
+
⋅
X2
OSCILLATOR
1 b1
ESTIMATED FREQUENCY
CRYSTAL
, connected from the X1
⋅
+
LOAD
1 b1
+
⋅
0.5 b0
(ATR = 011111) =
+
⋅
0.5 b0
PPM
0
+
⋅
9
LOAD
)pF
ISL12029, ISL12029A
+
9
⎞ pF
⎠
X1
,
(EQ. 1)
(EQ. 2)
and
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
“RESET” on page 9 and “Power Control Operation” on
page 16.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
options.
ISL12029A)
ISL12029)
See “Power Control Operation” on page 16 for more details.
Also see “I
LVR Operation” on page 25 for important details.
VTS2, VTS1, VTS0: V
The ISL12029 is shipped with a default V
(V
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12029 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The V
selection is via 3 bits (VTS2, VTS1 and VTS0) (see Table 6).
Care should be taken when changing the V
If the V
device will go into RESET and unless V
device will no longer be able to communicate using the I
bus.
Option 1 Standard Mode: Set “BSW = 0” (default for
Option 2 Legacy/Default Mode: Set “BSW = 1” (default for
RESET
DTR2
TABLE 5. DIGITAL TRIMMING REGISTERS (Continued)
0
0
0
1
1
1
1
RESET
DTR REGISTER
) per the ordering information table. This register is
2
C Communications During Battery Backup and
DTR1
voltage selected is higher than V
1
0
1
0
1
0
1
DD
DTR0
and Back Up Battery. There are two
RESET
0
1
1
0
0
1
1
Select Bits
ESTIMATED FREQUENCY
DD
DD
RESET
is increased, the
PPM
+10
+20
+30
threshold
-10
-20
-30
0
December 16, 2010
DD
select bits.
, then the
FN6206.10
RESET
2
C