CDP68HC68T1EZ Intersil, CDP68HC68T1EZ Datasheet - Page 13

• Manufacturer Part Number: CDP68HC68T1EZ
• Description: IC RTC 32X8 NVSRAM CMOS 16DIP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of CDP68HC68T1EZ

• Memory Size: 32B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 3 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STATUS REGISTER (Read Only) - Address 30H
NOTES:
Watchdog
If this bit is set high, the watchdog circuit has detected a
CPU failure.
Test Mode
When this bit is set high, the device is in the TEST MODE.
First-time Up
Power-on reset sets this bit high. This signifies that data in
the RAM and Clock is not valid and should be initialized.
Interrupt True
A high in this bit signifies that one of the three interrupts
(Power Sense, Alarm, and Clock) is valid.
Power-sense Interrupt
This bit set high signifies that the power-sense circuit has
generated an interrupt.
Alarm Interrupt
When the seconds, minutes and hours time and alarm
counter are equal, this bit will be set high. Status Register
must be read before loading Interrupt Control Register for
valid alarm indication after alarm activates.
Clock Interrupt
A periodic interrupt will set this bit high.
All bits are reset by a power-on reset except the “FIRST-
TIME UP” which is set. All bits except the power-sense bit
are reset after a read of this register.
10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE cycle.
9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register.
D7
0
DISABLE
RESET
WRITE
MODE
READ
WATCHDOG
D6
13
MODE
CE
TEST
H
H
L
D5
FIRST
TIME
CDP68HC68T1
UP
D4
INPUT DISABLED
TRUTH TABLE
SCK (Note 9)
CPOL = 1
CPOL = 0
CPOL = 1
CPOL = 0
INTERRUPT
Pin Signal Description
SCK (Serial Clock Input) (
This input causes serial data to be latched from the MOSI
input and shifted out on the MISO output.
MOSI (Master Out/Slave In) (
Data bytes are shifted in at this pin, most significant bit
(MSB) first.
MISO (Master In/Slave Out)
Data bytes are shifted out at this pin, most significant bit
(MSB) first.
CE (Chip Enable) (
A positive chip-enable input. A low level at this input holds
the serial interface logic in a reset state, and disables the
output driver at the MISO pin.
NOTES:
12. The CE input has as internal pull-down device, if the input is in a
11. These inputs will retain their previous state if the line driving them
TRUE
D3
goes into a High-Z state.
low state before going to High Z, the input can be left in a High Z.
SIGNAL
INPUT DISABLED
DATA BIT LATCH
INTERRUPT
POWER
SENSE
D2
MOSI
X
Note 12
)
INTERRUPT
Note 11
ALARM
Note 11
D1
)
NEXT DATA BIT
SHIFTED OUT
)
(Note 10)
HIGH Z
HIGH Z
MISO
INTERRUPT
October 29, 2007
CLOCK
D0
FN1547.8